Presentation 2020-11-17
Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder
Naoto Soga, Shimpei Sato, HIroki Nakahara,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Advancements in portable electrocardiographs have allowed electrocardiogram (ECG) signals to be recorded in everyday life. Machine-learning techniques, including deep learning, have been used in numerous studies to analyze ECG signals because they exhibit superior performance to conventional methods. However, deep-learning based models often have too many parameters to implement on mobile hardware, its amount of hardware is too large and dissipates much power consumption. We propose a design flow to implement the outlier detector using an autoencoder on a low-end FPGA. To shorten the preparation time of ECG data used in training an autoencoder, an unsupervised learning technique is applied. Additionally, to minimize the volume of the weight parameters, a weight sparseness technique is applied. Also, all the parameters are converted into fixed-point values, and weight sharing technique was applied to further reduce the weight parameter volume. We implemented the autoencoder on a Digilent Inc. ZedBoard and compared the results with those for the ARM mobile CPU for a built-in device. The results indicated that our FPGA implementation of the outlier detector was 12 times faster and 106 times more energy-efficient.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) outlier detection / autoencoder / unsupervised learning / FPGA
Paper # VLD2020-17,ICD2020-37,DC2020-37,RECONF2020-36
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF)

Conference Information
Committee VLD / DC / RECONF / ICD / IPSJ-SLDM
Conference Date 2020/11/17(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2020 -New Field of VLSI Design-
Chair Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Yuichi Nakamura(NEC)
Vice Chair Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(masafumi2.takahashi@kioxia.com)
Secretary Kazutoshi Kobayashi(Hitachi) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(Nihon Univ.) / Yoshiki Yamaguchi(Chiba Univ.) / Masafumi Takahashi(e-trees.Japan) / (NEC)
Assistant Takuma Nishimoto(Hitachi) / / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Koji Nii(TSMC) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder
Sub Title (in English)
Keyword(1) outlier detection
Keyword(2) autoencoder
Keyword(3) unsupervised learning
Keyword(4) FPGA
1st Author's Name Naoto Soga
1st Author's Affiliation Tokyo Institute of Technology(Tokyo Tech)
2nd Author's Name Shimpei Sato
2nd Author's Affiliation Tokyo Institute of Technology(Tokyo Tech)
3rd Author's Name HIroki Nakahara
3rd Author's Affiliation Tokyo Institute of Technology(Tokyo Tech)
Date 2020-11-17
Paper # VLD2020-17,ICD2020-37,DC2020-37,RECONF2020-36
Volume (vol) vol.120
Number (no) VLD-234,ICD-235,DC-236,RECONF-237
Page pp.pp.36-41(VLD), pp.36-41(ICD), pp.36-41(DC), pp.36-41(RECONF),
#Pages 6
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF)