Presentation | 2020-11-17 Design of Nonvolatile SRAM Using SONOS Flash Cell and its Evaluation by Circuit Simulation Takaki Urabe, Koji Nii, Kazutoshi Kobayashi, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, we designed a layout of a nonvolatile SRAM memory using the SONOS Flash memory, and investigated its characteristics. As a result of circuit simulations, the area of NV-SRAM increases by 47% compared to SRAM, but the operating speed increases by less than 1%. Because NV-SRAM can be turned off during standby, so the power consumptioncan be reduced if the standby time is 15% or more of the operating time. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | SRAM / Circuit Symulation / Nonvolatile memory / Break Even Time |
Paper # | VLD2020-11,ICD2020-31,DC2020-31,RECONF2020-30 |
Date of Issue | 2020-11-10 (VLD, ICD, DC, RECONF) |
Conference Information | |
Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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Conference Date | 2020/11/17(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Online |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2020 -New Field of VLSI Design- |
Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Yuichi Nakamura(NEC) |
Vice Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(masafumi2.takahashi@kioxia.com) |
Secretary | Kazutoshi Kobayashi(Hitachi) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(Nihon Univ.) / Yoshiki Yamaguchi(Chiba Univ.) / Masafumi Takahashi(e-trees.Japan) / (NEC) |
Assistant | Takuma Nishimoto(Hitachi) / / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Koji Nii(TSMC) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Design of Nonvolatile SRAM Using SONOS Flash Cell and its Evaluation by Circuit Simulation |
Sub Title (in English) | |
Keyword(1) | SRAM |
Keyword(2) | Circuit Symulation |
Keyword(3) | Nonvolatile memory |
Keyword(4) | Break Even Time |
1st Author's Name | Takaki Urabe |
1st Author's Affiliation | Kyoto Institute of Technology(KIT) |
2nd Author's Name | Koji Nii |
2nd Author's Affiliation | Kyoto Institute of Technology(KIT) |
3rd Author's Name | Kazutoshi Kobayashi |
3rd Author's Affiliation | Kyoto Institute of Technology(KIT) |
Date | 2020-11-17 |
Paper # | VLD2020-11,ICD2020-31,DC2020-31,RECONF2020-30 |
Volume (vol) | vol.120 |
Number (no) | VLD-234,ICD-235,DC-236,RECONF-237 |
Page | pp.pp.1-5(VLD), pp.1-5(ICD), pp.1-5(DC), pp.1-5(RECONF), |
#Pages | 5 |
Date of Issue | 2020-11-10 (VLD, ICD, DC, RECONF) |