Presentation | 2020-11-17 Analysis of Resistance Distribution in Chips with Inductive Coupling Wireless Communication Interface Hideto Kayashima, Hideharu Amano, Tsunaaki Shidei, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Building Block Computing Systems, one of the 3D stacked LSI systems, use a wireless communication interface TCI (Through Chip Interface) using electromagnetic induction between coils as an inter-chip communication technology. However, TCI needs more voltages than designed values and outputs lower operating frequencies than designed values. To solve this problem, we show the results of resistance distribution analysis for each chip with TCI. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Building block computing system / ThruChip Interface / 3-D stacked VLSIs |
Paper # | VLD2020-19,ICD2020-39,DC2020-39,RECONF2020-38 |
Date of Issue | 2020-11-10 (VLD, ICD, DC, RECONF) |
Conference Information | |
Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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Conference Date | 2020/11/17(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Online |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2020 -New Field of VLSI Design- |
Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Yuichi Nakamura(NEC) |
Vice Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(masafumi2.takahashi@kioxia.com) |
Secretary | Kazutoshi Kobayashi(Hitachi) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(Nihon Univ.) / Yoshiki Yamaguchi(Chiba Univ.) / Masafumi Takahashi(e-trees.Japan) / (NEC) |
Assistant | Takuma Nishimoto(Hitachi) / / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Koji Nii(TSMC) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Analysis of Resistance Distribution in Chips with Inductive Coupling Wireless Communication Interface |
Sub Title (in English) | |
Keyword(1) | Building block computing system |
Keyword(2) | ThruChip Interface |
Keyword(3) | 3-D stacked VLSIs |
1st Author's Name | Hideto Kayashima |
1st Author's Affiliation | Keio University(Keio Univ.) |
2nd Author's Name | Hideharu Amano |
2nd Author's Affiliation | Keio University(Keio Univ.) |
3rd Author's Name | Tsunaaki Shidei |
3rd Author's Affiliation | Keio University(Keio Univ.) |
Date | 2020-11-17 |
Paper # | VLD2020-19,ICD2020-39,DC2020-39,RECONF2020-38 |
Volume (vol) | vol.120 |
Number (no) | VLD-234,ICD-235,DC-236,RECONF-237 |
Page | pp.pp.48-53(VLD), pp.48-53(ICD), pp.48-53(DC), pp.48-53(RECONF), |
#Pages | 6 |
Date of Issue | 2020-11-10 (VLD, ICD, DC, RECONF) |