| Presentation | 2020-11-17 Power Analysis Based on Probability Calculation of Small Regions in LSI Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power consumption causes excessive IR-drop and excessive delay, resulting in test malfunction. Excessive IR-drop does not uniformly occur in the whole area of circuit, but in certain areas where many switching activities occur. Therefore, it is important for efficient reduction of excessive IR-drop to locate areas where many switching activities occur during LSI testing. In this work, we propose a method to locate areas where many switching activities occur by focusing on the probability calculation for the combination of several logic gates in LSI design data. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | at-speed testing / test power / IR-drop / transition delay test / test malfunction / probability of switching activity |
| Paper # | VLD2020-13,ICD2020-33,DC2020-33,RECONF2020-32 |
| Date of Issue | 2020-11-10 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2020/11/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2020 -New Field of VLSI Design- |
| Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(masafumi2.takahashi@kioxia.com) |
| Secretary | Kazutoshi Kobayashi(Hitachi) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(Nihon Univ.) / Yoshiki Yamaguchi(Chiba Univ.) / Masafumi Takahashi(e-trees.Japan) / (NEC) |
| Assistant | Takuma Nishimoto(Hitachi) / / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Koji Nii(TSMC) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Analysis Based on Probability Calculation of Small Regions in LSI |
| Sub Title (in English) | |
| Keyword(1) | at-speed testing |
| Keyword(2) | test power |
| Keyword(3) | IR-drop |
| Keyword(4) | transition delay test |
| Keyword(5) | test malfunction |
| Keyword(6) | probability of switching activity |
| 1st Author's Name | Ryo Oba |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Ryu Hoshino |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 3rd Author's Name | Kohei Miyase |
| 3rd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 4th Author's Name | Xiaoqing Wen |
| 4th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 5th Author's Name | Seiji Kajihara |
| 5th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2020-11-17 |
| Paper # | VLD2020-13,ICD2020-33,DC2020-33,RECONF2020-32 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-234,ICD-235,DC-236,RECONF-237 |
| Page | pp.pp.12-17(VLD), pp.12-17(ICD), pp.12-17(DC), pp.12-17(RECONF), |
| #Pages | 6 |
| Date of Issue | 2020-11-10 (VLD, ICD, DC, RECONF) |