| Presentation | 2020-10-01 An FPGA Implementation of Human Recognition using MRCoHOG Features Yuya Nagamine, Kazuki Yoshihiro, Masatoshi Shibata, Hideo Yamada, Shuichi Enokida, Hakaru Tamukoh, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this research, we design a hardware of human recognition using Multiresolution Co-occurrence Histograms of Oriented Gradients (MRCoHOG) features and implement to Field-Programmable Gate Array (FPGA) for accelerating it. We propose a pipelined architecture of classifier, based on binarized neural networks (BNN) to solve large memory resources of FPGA for storing features. We verified the effectiveness of the designed circuits for a binary classifier that recognizes an input image is human being or not for an image size of 32 times 64 pixels. Experimental results show that the proposed method reduces memory resources for storing features completely about compared with the ordinary method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Image Processing / Human Recognition / HOG / MRCoHOG / FPGA |
| Paper # | SIS2020-16 |
| Date of Issue | 2020-09-24 (SIS) |
| Conference Information | |
| Committee | SIS / ITE-BCT |
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| Conference Date | 2020/10/1(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Implementation Technology, Short Range Wireless Systems, Smart Multimedia Systems, Broadcasting Technology, etc. |
| Chair | Noriaki Suetake(Yamaguchi Univ.) / Kyoichi Saito(NHK) |
| Vice Chair | Tomoaki Kimura(Kanagawa Inst. of Tech.) / Naoto Sasaoka(Tottori Univ.) |
| Secretary | Tomoaki Kimura(Kindai Univ.) / Naoto Sasaoka(National Inst. of Tech., Ube College) / (NHK) |
| Assistant | Yukihiro Bandoh(NTT) / Soh Yoshida(Kansai Univ.) / Shigeki Shiokawa(Kanagawa Inst. of Tech.) / Shoichiro Sekiguchi(NHK) / Toshiharu Morizumi(NTT) / Toshimitsu Kobayashi(NBN) |
| Paper Information | |
| Registration To | Technical Committee on Smart Info-Media Systems / Technical Group on Broadcasting and Communication Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA Implementation of Human Recognition using MRCoHOG Features |
| Sub Title (in English) | |
| Keyword(1) | Image Processing |
| Keyword(2) | Human Recognition |
| Keyword(3) | HOG |
| Keyword(4) | MRCoHOG |
| Keyword(5) | FPGA |
| 1st Author's Name | Yuya Nagamine |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Kazuki Yoshihiro |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 3rd Author's Name | Masatoshi Shibata |
| 3rd Author's Affiliation | EQUOS RESEARCH Co., Ltd(EQUOS RESEARCH) |
| 4th Author's Name | Hideo Yamada |
| 4th Author's Affiliation | EQUOS RESEARCH Co., Ltd(EQUOS RESEARCH) |
| 5th Author's Name | Shuichi Enokida |
| 5th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 6th Author's Name | Hakaru Tamukoh |
| 6th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2020-10-01 |
| Paper # | SIS2020-16 |
| Volume (vol) | vol.120 |
| Number (no) | SIS-176 |
| Page | pp.pp.35-39(SIS), |
| #Pages | 5 |
| Date of Issue | 2020-09-24 (SIS) |