| Presentation | 2020-10-26 Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware Mitsufumi Yamazaki, Junichi Sakamoto, Tsutomu Matsumoto, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To reduce the latency of pairing calculation for advanced cryptography, hardware implementations with pipelined modular multipliers are effective. Because processing on a pipelined implementation is more complex than without it, that has a potential of resistance against power analysis attack. However, the detailed analyses have not been studied enough. This report discusses the potential that an attacker extracts secret information by power analysis attack with adequate inputs focusing pipeline scheduling to the targeted pairing hardware. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | advanced cryptography / pairing hardware / pipeline scheduling / power analysis attack / side-channel security |
| Paper # | HWS2020-26,ICD2020-15 |
| Date of Issue | 2020-10-19 (HWS, ICD) |
| Conference Information | |
| Committee | ICD / HWS |
|---|---|
| Conference Date | 2020/10/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Chair | Makoto Nagata(Kobe Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Masafumi Takahashi(masafumi2.takahashi@kioxia.com) / Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) |
| Secretary | Masafumi Takahashi(Socionext) / Yasuhisa Shimazaki(Osaka Univ.) / Makoto Nagata(Kyushu Univ.) |
| Assistant | Koji Nii(TSMC) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Hardware Security |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware |
| Sub Title (in English) | |
| Keyword(1) | advanced cryptography |
| Keyword(2) | pairing hardware |
| Keyword(3) | pipeline scheduling |
| Keyword(4) | power analysis attack |
| Keyword(5) | side-channel security |
| 1st Author's Name | Mitsufumi Yamazaki |
| 1st Author's Affiliation | Yokohama National University(YNU) |
| 2nd Author's Name | Junichi Sakamoto |
| 2nd Author's Affiliation | Yokohama National University(YNU) |
| 3rd Author's Name | Tsutomu Matsumoto |
| 3rd Author's Affiliation | Yokohama National University(YNU) |
| Date | 2020-10-26 |
| Paper # | HWS2020-26,ICD2020-15 |
| Volume (vol) | vol.120 |
| Number (no) | HWS-211,ICD-212 |
| Page | pp.pp.7-12(HWS), pp.7-12(ICD), |
| #Pages | 6 |
| Date of Issue | 2020-10-19 (HWS, ICD) |