Presentation 2020-10-26
Examination of requirements for power side-channel attack resistance evaluation boards of cryptographic integrated circuits
Tomonobu Kan, Kengo Iokibe, Yoshitaka Toyota,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) When evaluating the resistance of a cryptographic circuit to power analysis attacks by measurement, it is not easy to evaluate the IC alone, so the evaluation is performed by mounting the IC on the evaluation board. However, the evaluation board’s specifications are not defined, and even if the same IC is evaluated, the evaluation result may differ depending on the mounted evaluation board. Since it is not possible to determine which evaluation result is credible, it is necessary to unify the evaluation environment. In this study, we consider that side-channel information leakage depends on the transfer impedance, and the purpose is to determine the required specifications of the transfer impedance. In this paper, we show an example in which the evaluation results of side-channel attack resistance differ between the inside of the IC and the substrate, and confirm that the side-channel information leakage depends on the transmission impedance. Using two types of evaluation boards, SASEBO-G and SENPU, the correlation coefficient calculated from the SC leakage waveform measured at the measurement port on the evaluation board was about the same. SENPU, in contrast, had a larger correlation coefficient at the IC level that was calculated from the relational expression between SNR and the correlation coefficient. Comparing the amplitudes of the leaked waveforms, SASEBO-G was 18 times larger. We also calculated the transfer impedance based on the equivalent circuits of the power distribution networks of the FPGA core circuits of both boards. SASEBO-G was larger transfer impedances than SENPU. This result shows that the side-channel information leakage depends on the transfer impedance of the IC power distribution network.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Side-channel attack / Correlation power analysis / AES / Evaluation board / Signal to noise ratio (SNR) / Transfer impedance
Paper # HWS2020-25,ICD2020-14
Date of Issue 2020-10-19 (HWS, ICD)

Conference Information
Committee ICD / HWS
Conference Date 2020/10/26(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) Hardware Security, etc.
Chair Makoto Nagata(Kobe Univ.) / Makoto Ikeda(Univ. of Tokyo)
Vice Chair Masafumi Takahashi(masafumi2.takahashi@kioxia.com) / Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.)
Secretary Masafumi Takahashi(Socionext) / Yasuhisa Shimazaki(Osaka Univ.) / Makoto Nagata(Kyushu Univ.)
Assistant Koji Nii(TSMC) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.)

Paper Information
Registration To Technical Committee on Integrated Circuits and Devices / Technical Committee on Hardware Security
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Examination of requirements for power side-channel attack resistance evaluation boards of cryptographic integrated circuits
Sub Title (in English) PDN transfer impedance contributing to leakage strength
Keyword(1) Side-channel attack
Keyword(2) Correlation power analysis
Keyword(3) AES
Keyword(4) Evaluation board
Keyword(5) Signal to noise ratio (SNR)
Keyword(6) Transfer impedance
1st Author's Name Tomonobu Kan
1st Author's Affiliation Okayama University(Okayama Univ.)
2nd Author's Name Kengo Iokibe
2nd Author's Affiliation Okayama University(Okayama Univ.)
3rd Author's Name Yoshitaka Toyota
3rd Author's Affiliation Okayama University(Okayama Univ.)
Date 2020-10-26
Paper # HWS2020-25,ICD2020-14
Volume (vol) vol.120
Number (no) HWS-211,ICD-212
Page pp.pp.1-6(HWS), pp.1-6(ICD),
#Pages 6
Date of Issue 2020-10-19 (HWS, ICD)