Presentation	2020-09-11 An FPGA-Based Low-Latency Accelerator for Randomly Wired Convolutional Neural Networks Ryosuke Kuramochi, Hiroki Nakahara,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Convolutional neural networks(CNNs) are widely used for image tasks in both embedded systems and data centers. Particularly, when deploying CNNs in a data center, achieving high accuracy and low latency are important for various tasks. We propose an FPGA-based inference accelerator for randomly wired convolutional neural networks(RWCNNs), whose layer structures are based on random graph models. Because RWCNN can be processed in parallel, we can reduce the latency by concurrently using multiple computational units. We use the HBM2 to store feature maps, as multiple computational units need to simultaneously access different feature maps. In addition, the HBM channels and computational units are connected using a crossbar switch to efficiently transfer the feature maps. We allocate each layer to computational units using a simple heuristic algorithm. In addition, we allocate each layer to the HBM channels by coloring a conflict graph built based on the allocated schedule. This makes it possible for the computational units to access HBM channels in parallel. We implemented our accelerator on an Alveo U50 FPGA and compared it with a FPGA-based inference accelerator that targets ResNet-50. In the ImageNet image classification task, we could process an image in 16.6 ms, which is 43% lower than that for a conventional accelerator.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Deep Learning / CNN / FPGA / RWCNN
Paper #	RECONF2020-27
Date of Issue	2020-09-03 (RECONF)

Conference Information
Committee	RECONF
Conference Date	2020/9/10(2days)
Place (in Japanese)	(See Japanese page)
Place (in English)	Online
Topics (in Japanese)	(See Japanese page)
Topics (in English)	Reconfigurable system, etc.
Chair	Yuichiro Shibata(Nagasaki Univ.)
Vice Chair	Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.)
Secretary	Kentaro Sano(e-trees.Japan) / Yoshiki Yamaguchi(NEC)
Assistant	Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL)

Paper Information
Registration To	Technical Committee on Reconfigurable Systems
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	An FPGA-Based Low-Latency Accelerator for Randomly Wired Convolutional Neural Networks
Sub Title (in English)
Keyword(1)	Deep Learning
Keyword(2)	CNN
Keyword(3)	FPGA
Keyword(4)	RWCNN
1st Author's Name	Ryosuke Kuramochi
1st Author's Affiliation	Tokyo Institute of Technology(Tokyo Tech)
2nd Author's Name	Hiroki Nakahara
2nd Author's Affiliation	Tokyo Institute of Technology(Tokyo Tech)
Date	2020-09-11
Paper #	RECONF2020-27
Volume (vol)	vol.120
Number (no)	RECONF-168
Page	pp.pp.48-53(RECONF),
#Pages	6
Date of Issue	2020-09-03 (RECONF)