| Presentation | 2020-08-07 Gate-all-around p-type poly-Si junctionless nanowire transistor with steep subthreshold slope Min-Ju Ahn, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this work, GAA p-type junctionless nanowire transistor with BF2+ implanted poly-Si channel have been fabricated and evaluated. It exhibits excellent subthreshold slope (SS) close to ideal SS value as well as high on/off current ratio and low off-current. It is mainly attributted to that fluorine ions introduced during BF2+ implantation can produce high quaility of poly-Si channel by effectively passivating grain boundary defects, and segregation of boron ions during high temperature channel thinning process, which results in larger grain size (reduced grain boundary defects) and reduced channel concentration. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Gate-all-around / Junctionless / Poly-Si / Fluorine passivation |
| Paper # | SDM2020-9,ICD2020-9 |
| Date of Issue | 2020-07-30 (SDM, ICD) |
| Conference Information | |
| Committee | ICD / SDM / ITE-IST |
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| Conference Date | 2020/8/6(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Makoto Nagata(Kobe Univ.) / Hiroshige Hirano(TowerJazz Panasonic) / Junichi Akita(Kanazawa Univ.) |
| Vice Chair | Masafumi Takahashi(Toshiba-memory) / Shunichiro Ohmi(Tokyo Inst. of Tech.) / 池辺 将之(北大) / 廣瀬 裕(パナソニック) |
| Secretary | Masafumi Takahashi(Socionext) / Shunichiro Ohmi(Osaka Univ.) / 池辺 将之(AIST) / 廣瀬 裕(Nihon Univ.) |
| Assistant | Koji Nii(Floadia) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.) / Taiji Noda(Panasonic) / Tomoyuki Suwa(Tohoku Univ.) / 小室 孝(埼玉大) / 下ノ村 和弘(立命館大) / 香川 景一郞(静岡大) / 徳田 崇(東工大) / 黒田 理人(東北大) / 船津 良平(NHK) / 山下 雄一郎(TSMC) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Gate-all-around p-type poly-Si junctionless nanowire transistor with steep subthreshold slope |
| Sub Title (in English) | |
| Keyword(1) | Gate-all-around |
| Keyword(2) | Junctionless |
| Keyword(3) | Poly-Si |
| Keyword(4) | Fluorine passivation |
| 1st Author's Name | Min-Ju Ahn |
| 1st Author's Affiliation | Institute of Industrial Science, The University of Tokyo(IIS, Tokyo Univ.) |
| 2nd Author's Name | Takuya Saraya |
| 2nd Author's Affiliation | Institute of Industrial Science, The University of Tokyo(IIS, Tokyo Univ.) |
| 3rd Author's Name | Masaharu Kobayashi |
| 3rd Author's Affiliation | Institute of Industrial Science, The University of Tokyo(IIS, Tokyo Univ.) |
| 4th Author's Name | Toshiro Hiramoto |
| 4th Author's Affiliation | Institute of Industrial Science, The University of Tokyo(IIS, Tokyo Univ.) |
| Date | 2020-08-07 |
| Paper # | SDM2020-9,ICD2020-9 |
| Volume (vol) | vol.120 |
| Number (no) | SDM-126,ICD-127 |
| Page | pp.pp.41-46(SDM), pp.41-46(ICD), |
| #Pages | 6 |
| Date of Issue | 2020-07-30 (SDM, ICD) |