Presentation 2020-08-06
Over-the-top Si Interposer Embedding Backside Buried Metal to Reduce Power Supply Impedance
Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 2.5D structure with a Si interposer stacked on a CMOS chip is developed to reduce power supply impedance. A backside buried metal (BBM) in Si interposer provides low resistive wiring of power / ground nodes and also forms a large parasitic bypass capacitance between power and ground patterns, which drastically suppresses the power supply noise. The Si interposer was implemented over a cryptographic chip with a large scale digital circuit fabricated in 130 nm CMOS. The measured resistance values of power and ground line were reduced by 30% and 56%, respectively, and the measured bypass capacitance was increased by 2.4 nF, owing to the additional low resistive wiring in parallel and a large parasitic capacitance of the Si interposer and the stacking structure itself. An internal noise monitoring circuit embedded in the CMOS chip indicates that the proposed over-the-top Si interposer reduces a peak-to-peak power supply noise and DC drop during cryptographic operation to less than 50%.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) 2.5D implementation / Si interposer / Power supply impedance / Cryptographic circuit
Paper # SDM2020-5,ICD2020-5
Date of Issue 2020-07-30 (SDM, ICD)

Conference Information
Committee ICD / SDM / ITE-IST
Conference Date 2020/8/6(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications
Chair Makoto Nagata(Kobe Univ.) / Hiroshige Hirano(TowerJazz Panasonic) / Junichi Akita(Kanazawa Univ.)
Vice Chair Masafumi Takahashi(Toshiba-memory) / Shunichiro Ohmi(Tokyo Inst. of Tech.) / 池辺 将之(北大) / 廣瀬 裕(パナソニック)
Secretary Masafumi Takahashi(Socionext) / Shunichiro Ohmi(Osaka Univ.) / 池辺 将之(AIST) / 廣瀬 裕(Nihon Univ.)
Assistant Koji Nii(Floadia) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.) / Taiji Noda(Panasonic) / Tomoyuki Suwa(Tohoku Univ.) / 小室 孝(埼玉大) / 下ノ村 和弘(立命館大) / 香川 景一郞(静岡大) / 徳田 崇(東工大) / 黒田 理人(東北大) / 船津 良平(NHK) / 山下 雄一郎(TSMC)

Paper Information
Registration To Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Over-the-top Si Interposer Embedding Backside Buried Metal to Reduce Power Supply Impedance
Sub Title (in English)
Keyword(1) 2.5D implementation
Keyword(2) Si interposer
Keyword(3) Power supply impedance
Keyword(4) Cryptographic circuit
1st Author's Name Takuji Miki
1st Author's Affiliation Kobe University(Kobe Univ.)
2nd Author's Name Makoto Nagata
2nd Author's Affiliation Kobe University(Kobe Univ.)
3rd Author's Name Akihiro Tsukioka
3rd Author's Affiliation Kobe University(Kobe Univ.)
4th Author's Name Noriyuki Miura
4th Author's Affiliation Osaka University(Osaka Univ.)
5th Author's Name Takaaki Okidono
5th Author's Affiliation ECSEC(ECSEC)
6th Author's Name Yuuki Araga
6th Author's Affiliation AIST(AIST)
7th Author's Name Naoya Watanabe
7th Author's Affiliation AIST(AIST)
8th Author's Name Haruo Shimamoto
8th Author's Affiliation AIST(AIST)
9th Author's Name Katsuya Kikuchi
9th Author's Affiliation AIST(AIST)
Date 2020-08-06
Paper # SDM2020-5,ICD2020-5
Volume (vol) vol.120
Number (no) SDM-126,ICD-127
Page pp.pp.19-24(SDM), pp.19-24(ICD),
#Pages 6
Date of Issue 2020-07-30 (SDM, ICD)