Presentation 2020-07-30
Instruction Prefetcher focusing on properties of Prefetch Distance
Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Instruction cache misses and branch target buffer (BTB) misses are performance bottlenecks in recent applications, and many instruction prefetchers have been proposed to eliminate them. In order for these prefetchers to work effectively, it isimportant to issue prefetch at a sufficiently early timing using a long prefetch distance. In addition, we found that increasingthe prefetch distance improves not only the prefetch timing but also the coverage. Therefore, we propose a D-JOLT prefetcherthat takes advantage of a large prefetch distance. D-JOLT is a prefetcher that learns and prediction by signatures using theinformation of function calls. D-JOLT achieves highly accurate prediction of a distant future with a hybrid configuration ofprefetchers with different prediction accuracy and a signature that uses the number of consecutive return instructions. Weevaluated D-JOLT with traces distributed in The First Instruction Prefetching Championship, and D-JOLT achieves a 52.0%performance improvement over a processor without an instruction prefetching and a 21.5% performance improvement over thestate of the art prefetcher.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) prefetching / instruction cache / branch target buffer
Paper # CPSY2020-1,DC2020-1
Date of Issue 2020-07-23 (CPSY, DC)

Conference Information
Committee CPSY / DC / IPSJ-ARC
Conference Date 2020/7/30(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) SWoPP2020: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing
Chair Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Takahashi(Ehime Univ.) / Hiroshi Inoue(Kyushu Univ.)
Vice Chair Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Tatsuhiro Tsuchiya(Osaka Univ.)
Secretary Michihiro Koibuchi(Hokkaido Univ.) / Kota Nakajima(Nagoya Inst. of Tech.) / Tatsuhiro Tsuchiya(Nihon Univ.) / (Chiba Univ.)
Assistant Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo)

Paper Information
Registration To Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Instruction Prefetcher focusing on properties of Prefetch Distance
Sub Title (in English)
Keyword(1) prefetching
Keyword(2) instruction cache
Keyword(3) branch target buffer
1st Author's Name Tomoki Nakamura
1st Author's Affiliation The University of Tokyo(UTokyo)
2nd Author's Name Toru Koizumi
2nd Author's Affiliation The University of Tokyo(UTokyo)
3rd Author's Name Yuya Degawa
3rd Author's Affiliation The University of Tokyo(UTokyo)
4th Author's Name Hidetsugu Irie
4th Author's Affiliation The University of Tokyo(UTokyo)
5th Author's Name Shuichi Sakai
5th Author's Affiliation The University of Tokyo(UTokyo)
6th Author's Name Ryota Shioya
6th Author's Affiliation The University of Tokyo(UTokyo)
Date 2020-07-30
Paper # CPSY2020-1,DC2020-1
Volume (vol) vol.120
Number (no) CPSY-121,DC-122
Page pp.pp.1-8(CPSY), pp.1-8(DC),
#Pages 8
Date of Issue 2020-07-23 (CPSY, DC)