| Presentation | 2020-07-31 A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increased, and test generation methods for fault models in cells and test generation methods for gate-exhaustive fault models have been proposed. Since the number of gate-exhaustive faults is defined as the total sum of 2 to the power of the number of cell inputs, the number of faults and the number of test patterns drastically increase compared to the stuck-at fault model. In this paper, to reduce the number of test patterns, we propose a multiple target test generation method that enables detection of as many gate-exhaustive faults as possible with one test pattern during test generation. The proposed method was able to detect all detectable gate-exhaustive faults and to reduce the number of test patterns by 19 to 48% compared to the conventional method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | gate-exhaustive faults / multiple target fault test generation / test compaction / independent fault sets / Partial MaxSAT |
| Paper # | CPSY2020-12,DC2020-12 |
| Date of Issue | 2020-07-23 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
|---|---|
| Conference Date | 2020/7/30(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | SWoPP2020: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing |
| Chair | Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Takahashi(Ehime Univ.) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Tatsuhiro Tsuchiya(Osaka Univ.) |
| Secretary | Michihiro Koibuchi(Hokkaido Univ.) / Kota Nakajima(Nagoya Inst. of Tech.) / Tatsuhiro Tsuchiya(Nihon Univ.) / (Chiba Univ.) |
| Assistant | Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns |
| Sub Title (in English) | |
| Keyword(1) | gate-exhaustive faults |
| Keyword(2) | multiple target fault test generation |
| Keyword(3) | test compaction |
| Keyword(4) | independent fault sets |
| Keyword(5) | Partial MaxSAT |
| 1st Author's Name | Ryuki Asami |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Masayoshi Yoshimura |
| 3rd Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ.) |
| 4th Author's Name | Masayuki Arai |
| 4th Author's Affiliation | Nihon University(Nihon Univ.) |
| Date | 2020-07-31 |
| Paper # | CPSY2020-12,DC2020-12 |
| Volume (vol) | vol.120 |
| Number (no) | CPSY-121,DC-122 |
| Page | pp.pp.75-80(CPSY), pp.75-80(DC), |
| #Pages | 6 |
| Date of Issue | 2020-07-23 (CPSY, DC) |