| Presentation | 2020-05-28 ベイジアンネットワーク構造学習の演算回路の繰り返し利用によるFPGAアクセラレータ Yasuhiro Nitta, Hideki Takase, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A Bayesian network is one of the graphical models that represent the causality or correlation of multiple observed phenomena. The structure learning of this network is generally NP difficult, and the computational time to obtain an approximate solution becomes huge. This paper proposes an FPGA accelerator for structure learning of Bayesian networks. The proposed method employs a dataflow type architecture and executes processes without dependency in dynamic programming in parallel. By iteratively using processing elements at each processing stage, we can efficiently use limited resources while taking advantage of the parallel performance of FPGAs. We implemented the proposed method for Xilinx Alveo U200 using high-level synthesis. Evaluation results showed that we achieved up to 12.6 times faster than single-core execution of software and up to 2.98 times faster than on multi-core execution. The power consumption of the entire system was 11 % less than single-core execution and 41 % less than multi-core execution. Furthermore, in the structure learning of a practical network with 37 nodes, we applied the proposed method to the Local-to-Global algorithm and achieves 8.6 times faster than the software execution. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / bayesian network / structure learning / codesign |
| Paper # | RECONF2020-7 |
| Date of Issue | 2020-05-21 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2020/5/28(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Meeting room on Web |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Chair | Yuichiro Shibata(Nagasaki Univ.) |
| Vice Chair | Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) |
| Secretary | Kentaro Sano(Hiroshima City Univ.) / Yoshiki Yamaguchi(e-trees.Japan) |
| Assistant | Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | bayesian network |
| Keyword(3) | structure learning |
| Keyword(4) | codesign |
| 1st Author's Name | Yasuhiro Nitta |
| 1st Author's Affiliation | Kyoto University(Kyoto Univ.) |
| 2nd Author's Name | Hideki Takase |
| 2nd Author's Affiliation | Kyoto University/JST PRESTO(Kyoto Univ./JST) |
| Date | 2020-05-28 |
| Paper # | RECONF2020-7 |
| Volume (vol) | vol.120 |
| Number (no) | RECONF-36 |
| Page | pp.pp.37-42(RECONF), |
| #Pages | 6 |
| Date of Issue | 2020-05-21 (RECONF) |