| Presentation | 2020-03-06 On evaluation of logic locking method based on Affine transformation Yusuke Matsunaga, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | VLD2019-132,HWS2019-105 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On evaluation of logic locking method based on Affine transformation |
| Sub Title (in English) | |
| Keyword(1) | |
| 1st Author's Name | Yusuke Matsunaga |
| 1st Author's Affiliation | Kyushu University(Kyushu Univ.) |
| Date | 2020-03-06 |
| Paper # | VLD2019-132,HWS2019-105 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.221-225(VLD), pp.221-225(HWS), |
| #Pages | 5 |
| Date of Issue | 2020-02-26 (VLD, HWS) |