| Presentation | 2020-03-04 A Study of Arithmetic-Oriented Application Implementations for Via-Switch FPGA Takashi Imagawa, Yu Jaehoon, Masanori Hashimoto, Hiroyuki Ochi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Via-Switch FPGAs have different features from conventional SRAM-based FPGAs. It is necessary to build the application circuit implementation methodology and technology mapping algorithm in consideration of their difference. In this paper, we compare typical arithmetic-operation-based application circuits, such as matrix multiplication and FFT, implemented by different technology mapping policies, and report the differences in the number of computation resources and the number of their fan-outs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Via-Switch FPGA / technology mapping |
| Paper # | VLD2019-98,HWS2019-71 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
|---|---|
| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of Arithmetic-Oriented Application Implementations for Via-Switch FPGA |
| Sub Title (in English) | |
| Keyword(1) | Via-Switch FPGA |
| Keyword(2) | technology mapping |
| 1st Author's Name | Takashi Imagawa |
| 1st Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 2nd Author's Name | Yu Jaehoon |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Masanori Hashimoto |
| 3rd Author's Affiliation | Osaka University(Osaka Univ.) |
| 4th Author's Name | Hiroyuki Ochi |
| 4th Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| Date | 2020-03-04 |
| Paper # | VLD2019-98,HWS2019-71 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.25-29(VLD), pp.25-29(HWS), |
| #Pages | 5 |
| Date of Issue | 2020-02-26 (VLD, HWS) |