| Presentation | 2020-03-04 Gate Sizing for Programmable Delay Elements on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock tree before the fabrication and sets the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. In an existing design flow, since fanout of PDE is not taken into consideration, the cell with the highest drive ability and the highest power consumption is assigned into the gate in the last level of each PDE. Therefore, the area of the circuit obtained by the existing method is large, and the power consumption is high. In this paper, we propose a gate sizing method of PDEs considering fanout. The proposed method determines an initial gate size for each gate according to its fanout and adapts the modification of gate size based on delay analysis. The proposed method assigns the cell with appropriate drive ability into each gate. Experiments show reduction of circuit area and power consumption, and improvement of yield. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Post-silicon delay tuning / yield improvement / power reduction / Programmable Delay Element （PDE） / gate sizing |
| Paper # | VLD2019-103,HWS2019-76 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Gate Sizing for Programmable Delay Elements on Post-Silicon Delay Tuning |
| Sub Title (in English) | |
| Keyword(1) | Post-silicon delay tuning |
| Keyword(2) | yield improvement |
| Keyword(3) | power reduction |
| Keyword(4) | Programmable Delay Element （PDE） |
| Keyword(5) | gate sizing |
| 1st Author's Name | Kota Muroi |
| 1st Author's Affiliation | The University of Aizu(UoA) |
| 2nd Author's Name | Yukihide Kohira |
| 2nd Author's Affiliation | The University of Aizu(UoA) |
| Date | 2020-03-04 |
| Paper # | VLD2019-103,HWS2019-76 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.53-58(VLD), pp.53-58(HWS), |
| #Pages | 6 |
| Date of Issue | 2020-02-26 (VLD, HWS) |