| Presentation | 2020-03-06 Fundamental Study on Fault Analysis with Non-Uniform Faulty Values Caused at Fault Injection into Sequential Circuit Takumi Okamoto, Daisuke Fujimoto, Kazuo Sakiyama, Li Yang, Yu-ichi Hayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Fault analysis for the cryptographic module is roughly divided into two phases; those are injecting transient faults and analysis of faulty outputs. In methods of injecting faults, especially clock glitches, have been frequently used in previous researches. This method has mainly focused on faults caused by setup time violations due to the combinational circuit delay. Since characteristics of faulty outputs due to setup time violations depends on the implementation of combination circuits, the suitable analysis methods for each faulty outputs were proposed. On the other hands, in this paper, we consider the faults caused by time violation on the input of sequential circuits and discuss the possibility of extracting secret keys from the faulty outputs. If the above fault analysis is feasible, we do not need to pay attention to the differences in implementation methods of combination circuits. Because the trend of faulty ciphertexts only depends on the input threshold of sequential circuits and the characteristic of signal rising and falling. In the experiment, after the proposed fault injection method applies to 3 different implementations of the Advanced Encryption Standard (AES), the same analysis method is used to each faulty outputs and demonstrated that a secret key could be extracted; the effectiveness of the proposed method will be shown. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Fault Analysis / Sequential Circuit / Timing Violation |
| Paper # | VLD2019-128,HWS2019-101 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fundamental Study on Fault Analysis with Non-Uniform Faulty Values Caused at Fault Injection into Sequential Circuit |
| Sub Title (in English) | |
| Keyword(1) | Fault Analysis |
| Keyword(2) | Sequential Circuit |
| Keyword(3) | Timing Violation |
| 1st Author's Name | Takumi Okamoto |
| 1st Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 2nd Author's Name | Daisuke Fujimoto |
| 2nd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 3rd Author's Name | Kazuo Sakiyama |
| 3rd Author's Affiliation | The University of Electro- Communications(UEC) |
| 4th Author's Name | Li Yang |
| 4th Author's Affiliation | The University of Electro- Communications(UEC) |
| 5th Author's Name | Yu-ichi Hayashi |
| 5th Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| Date | 2020-03-06 |
| Paper # | VLD2019-128,HWS2019-101 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.197-201(VLD), pp.197-201(HWS), |
| #Pages | 5 |
| Date of Issue | 2020-02-26 (VLD, HWS) |