| Presentation | 2020-03-06 A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semiconductor technologies, it is increasing in defects whose detection is difficult in testing using conventional fault models. One of such defects is modeled by resistive open fault model. Resistive open faults represent degradation in conductivity within circuit's interconnects and result in small delay faults that causing timing failures. Hence, it is important to generate test patterns consider longest possible path. The size of an additional delay at a resistive open fault is determined by the logic values at the adjacent lines and the length of the adjacent lines. Therefore, it is important to fault propagation paths and adjacent lines in test generation for resistive open faults. In this paper, we propose a test generation method for resistive open faults which considers fault propagation paths and the number of reversed phase transitions on adjacent lines using Partial MaxSAT. Moreover, we evaluate the generated test set using a fault simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | resistive open faults / Partial MaxSAT / test generation / adjacent lines |
| Paper # | VLD2019-131,HWS2019-104 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver |
| Sub Title (in English) | |
| Keyword(1) | resistive open faults |
| Keyword(2) | Partial MaxSAT |
| Keyword(3) | test generation |
| Keyword(4) | adjacent lines |
| 1st Author's Name | Hiroshi Yamazaki |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Yuta Ishiyama |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Tatsuma Matsuta |
| 3rd Author's Affiliation | Nihon University(Nihon Univ.) |
| 4th Author's Name | Toshinori Hosokawa |
| 4th Author's Affiliation | Nihon University(Nihon Univ.) |
| 5th Author's Name | Masayoshi Yoshimura |
| 5th Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ.) |
| 6th Author's Name | Masayuki Arai |
| 6th Author's Affiliation | Nihon University(Nihon Univ.) |
| 7th Author's Name | Hiroyuki Yotsuyanagi |
| 7th Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 8th Author's Name | Masaki Hashizume |
| 8th Author's Affiliation | Tokushima University(Tokushima Univ.) |
| Date | 2020-03-06 |
| Paper # | VLD2019-131,HWS2019-104 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.215-220(VLD), pp.215-220(HWS), |
| #Pages | 6 |
| Date of Issue | 2020-02-26 (VLD, HWS) |