Presentation 2020-03-04
Estimation method of process variation using an IDDQ test and retention characteristics of flip-flop
Shinichi Nishizawa, Kazuhito,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # VLD2019-102,HWS2019-75
Date of Issue 2020-02-26 (VLD, HWS)

Conference Information
Committee HWS / VLD
Conference Date 2020/3/4(4days)
Place (in Japanese) (See Japanese page)
Place (in English) Okinawa Ken Seinen Kaikan
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc.
Chair Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.)
Vice Chair Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.)
Secretary Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu)
Assistant / Kazuki Ikeda(Hitachi)

Paper Information
Registration To Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Estimation method of process variation using an IDDQ test and retention characteristics of flip-flop
Sub Title (in English)
Keyword(1)
1st Author's Name Shinichi Nishizawa
1st Author's Affiliation Fukuoka University(Fukuoka Univ.)
2nd Author's Name Kazuhito
2nd Author's Affiliation Ito(Saitama Univ.)
Date 2020-03-04
Paper # VLD2019-102,HWS2019-75
Volume (vol) vol.119
Number (no) VLD-443,HWS-444
Page pp.pp.49-52(VLD), pp.49-52(HWS),
#Pages 4
Date of Issue 2020-02-26 (VLD, HWS)