| Presentation | 2020-03-07 Side-channel leakage evaluation of cryptographic module by IC chip level power supply noise simulation Kazuki Yasuda, Kazuki Monta, Akihiro Tsukioka, Noriyuki Miura, Makoto Nagata, Karthik Srinivasan, Shan Wan, Lagn Lin, Ying-Shiun Li, Norman Chang, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this research, we focused on power supply noise as one of the observed side channel information leakage in cryptographic modules using semiconductor integrated circuit (Ic chip) technology. The current consumption model by circuit operation and the power supply network model of the circuit are combined, and the result of analysis by the power supply noise simulation at the chip level is reported. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | IC chip / Power Noise / Crypto Modules / Side-channel leakage / supply noise simulation |
| Paper # | VLD2019-142,HWS2019-115 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Side-channel leakage evaluation of cryptographic module by IC chip level power supply noise simulation |
| Sub Title (in English) | |
| Keyword(1) | IC chip |
| Keyword(2) | Power Noise |
| Keyword(3) | Crypto Modules |
| Keyword(4) | Side-channel leakage |
| Keyword(5) | supply noise simulation |
| 1st Author's Name | Kazuki Yasuda |
| 1st Author's Affiliation | Kobe University(Kobe Univ) |
| 2nd Author's Name | Kazuki Monta |
| 2nd Author's Affiliation | Kobe University(Kobe Univ) |
| 3rd Author's Name | Akihiro Tsukioka |
| 3rd Author's Affiliation | Kobe University(Kobe Univ) |
| 4th Author's Name | Noriyuki Miura |
| 4th Author's Affiliation | Kobe University(Kobe Univ) |
| 5th Author's Name | Makoto Nagata |
| 5th Author's Affiliation | Kobe University(Kobe Univ) |
| 6th Author's Name | Karthik Srinivasan |
| 6th Author's Affiliation | ANSYS(ANSYS) |
| 7th Author's Name | Shan Wan |
| 7th Author's Affiliation | ANSYS(ANSYS) |
| 8th Author's Name | Lagn Lin |
| 8th Author's Affiliation | ANSYS(ANSYS) |
| 9th Author's Name | Ying-Shiun Li |
| 9th Author's Affiliation | ANSYS(ANSYS) |
| 10th Author's Name | Norman Chang |
| 10th Author's Affiliation | ANSYS(ANSYS) |
| Date | 2020-03-07 |
| Paper # | VLD2019-142,HWS2019-115 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.279-282(VLD), pp.279-282(HWS), |
| #Pages | 4 |
| Date of Issue | 2020-02-26 (VLD, HWS) |