| Presentation | 2020-03-05 stochasitc fast estimation of timing error induced circuit lifetime distribution Hazuki Tomiyama, Yutaka Masuda, Tohru Ishihara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In VLSI design, a designer needs the integrated circuit to keep correct operation under area, power, and performance constraints. For satisfying such constraints, a conventional logic simulator has been used. On theother hand, due to recent continuous process minitualization, the logic simulator suffers from its slow computationsince the circuit tends to have larger scale and becomes complex. This paper proposes a stochastic simulator thatestimates the circuit lifetime which is denoted as the time when timing error occurs. Our proposed simulator focuseson the important events, such as the activation of critical paths, and evaluates these events in a stochasitic way. Thanks to the aggregation of events and these stochastic treatment, the number of event occurrent can be dramaticallyreduced, which directly saves the computational time for lifetime estimation. This paper first implementsprototype of stochasitc simulator and compares the computational time and accuracy of lifetime estimation betweenthe prototype and logic simulator. Then, this work speeds up the prototype by further reducing the number ofevents with Poisson process. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | circuit lifetime / logic simulator / stochastic simulator |
| Paper # | VLD2019-113,HWS2019-86 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | stochasitc fast estimation of timing error induced circuit lifetime distribution |
| Sub Title (in English) | |
| Keyword(1) | circuit lifetime |
| Keyword(2) | logic simulator |
| Keyword(3) | stochastic simulator |
| 1st Author's Name | Hazuki Tomiyama |
| 1st Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 2nd Author's Name | Yutaka Masuda |
| 2nd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 3rd Author's Name | Tohru Ishihara |
| 3rd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| Date | 2020-03-05 |
| Paper # | VLD2019-113,HWS2019-86 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.113-118(VLD), pp.113-118(HWS), |
| #Pages | 6 |
| Date of Issue | 2020-02-26 (VLD, HWS) |