| Presentation | 2020-03-04 A Study of Dynamic Power Optimization by Latch Insertion for Asynchronous RTL Models Shogo Semba, Hiroshi Saito, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a dynamic power optimization method by latch insertion for asynchronous RTL models. In data-paths of the asynchronous RTL model, the proposed method inserts latches before combinational circuits to prevent the unnecessary operations. We also study a latch insertion by considering critical path delays to satisfy latency constraint. In the experiment, we applied the proposed method for three benchmarks and evaluated the reduction effect of dynamic power consumption. Compared to synchronous circuits with traditional operand isolations, the proposed latch insertion method reduced the dynamic power consumption by 28.2% on the average. On the other hand, the latch insertion method by considering critical path delays reduced the dynamic power consumption by 11.5% on the average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | asynchronous circuits / RTL / dynamic power consumption / operand isolation |
| Paper # | VLD2019-100,HWS2019-73 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of Dynamic Power Optimization by Latch Insertion for Asynchronous RTL Models |
| Sub Title (in English) | |
| Keyword(1) | asynchronous circuits |
| Keyword(2) | RTL |
| Keyword(3) | dynamic power consumption |
| Keyword(4) | operand isolation |
| 1st Author's Name | Shogo Semba |
| 1st Author's Affiliation | The University of Aizu(UoA) |
| 2nd Author's Name | Hiroshi Saito |
| 2nd Author's Affiliation | The University of Aizu(UoA) |
| Date | 2020-03-04 |
| Paper # | VLD2019-100,HWS2019-73 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.37-42(VLD), pp.37-42(HWS), |
| #Pages | 6 |
| Date of Issue | 2020-02-26 (VLD, HWS) |