| Presentation | 2020-03-05 Approximate Floating Point Multiplier based on Shifting Addition Using Carry Signal from Second-Highest-Bit Jie Li, Yi Guo, Shinji Kimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Approximate computing (AC) sacrifices accuracy for better hardware performance since it relaxes the requirement of exact equivalence between the specification and implementation [1]. Floating point multiplier is widely used nowadays but it consumes a large amount of hardware resources. In this paper, approximate computing is applied to floating point multiplier. We separate the mantissa part. Exact multiplication is used for higher bits and a shifting addition algorithm is applied to lower bits. The addition algorithm involves bit addition and bit shifting, which is much simpler than bit multiplication. Bit shifting process uses the specific carry signal. Some bits of the mantissa are truncated with a small loss of accuracy. The result shows that the mean accuracy of the proposed floating point multiplier is 99.17% and the lowest accuracy performs as 97.15% which can be accepted by a wide range of applications. Compared with the exact floating point multiplier, the proposed work can reduce 67.65% of area, 16.64% of delay and 75.62% of power, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Approximate computingfloating point multiplierhigh accuracy |
| Paper # | VLD2019-120,HWS2019-93 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Approximate Floating Point Multiplier based on Shifting Addition Using Carry Signal from Second-Highest-Bit |
| Sub Title (in English) | |
| Keyword(1) | Approximate computingfloating point multiplierhigh accuracy |
| 1st Author's Name | Jie Li |
| 1st Author's Affiliation | Waseda University(Waseda Univ.) |
| 2nd Author's Name | Yi Guo |
| 2nd Author's Affiliation | Waseda University(Waseda Univ.) |
| 3rd Author's Name | Shinji Kimura |
| 3rd Author's Affiliation | Waseda University(Waseda Univ.) |
| Date | 2020-03-05 |
| Paper # | VLD2019-120,HWS2019-93 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.151-156(VLD), pp.151-156(HWS), |
| #Pages | 6 |
| Date of Issue | 2020-02-26 (VLD, HWS) |