| Presentation | 2020-03-04 An EVBDD-based Design Verification for Elementary Function Generators Hiroto Fukuhara, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a design verification based on edge-valued binary decisiondiagrams (EVBDDs) for elementary function generators. In the proposed method, target circuits are compactly represetend by EVBDDs, and the maximum errors of the circuits are computed by comparing with EVBDDsrepresenting design specifications (i.e., reference models). We can formally verify elementary function generators by making sure if themaximum errors are tolerable. To efficiently generate EVBDDs from the target circuits, this paper alsopresents some arithmetic operation algorithms for EVBDDs that correspondsto arithmetic operations in the circuits. Experimental results show the efficiency of the proposed verification method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | EVBDD / design verification of elementary function generators / formal verification / graph operations |
| Paper # | VLD2019-96,HWS2019-69 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2020/3/4(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu) |
| Assistant | / Kazuki Ikeda(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An EVBDD-based Design Verification for Elementary Function Generators |
| Sub Title (in English) | |
| Keyword(1) | EVBDD |
| Keyword(2) | design verification of elementary function generators |
| Keyword(3) | formal verification |
| Keyword(4) | graph operations |
| 1st Author's Name | Hiroto Fukuhara |
| 1st Author's Affiliation | Hiroshima City University(HCU) |
| 2nd Author's Name | Shinobu Nagayama |
| 2nd Author's Affiliation | Hiroshima City University(HCU) |
| 3rd Author's Name | Masato Inagi |
| 3rd Author's Affiliation | Hiroshima City University(HCU) |
| 4th Author's Name | Shin'ichi Wakabayashi |
| 4th Author's Affiliation | Hiroshima City University(HCU) |
| Date | 2020-03-04 |
| Paper # | VLD2019-96,HWS2019-69 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-443,HWS-444 |
| Page | pp.pp.13-18(VLD), pp.13-18(HWS), |
| #Pages | 6 |
| Date of Issue | 2020-02-26 (VLD, HWS) |