| Presentation | 2020-03-03 A design and implementation of an HBM-based packet scheduler Katsushi Kobayashi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Although only DRAM can realize buffer sizes required by packet schedulers in Internet routers, it is obvious that existing its bandwidth capacities cannot satisfy the bandwidths growth in the future. High Bandwidth Memory (HBM) that significantly improves DRAM bandwidth throughputs by using silicon die stacking is emerging in the market. This report presents a design and implementation of an HBM-based packet scheduler on FPGA. Our HBM based scheduler implementation performed 75% of theoretical bandwidth of the HBM. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Internet / Packet Scheduler / Memory Technology |
| Paper # | SITE2019-94,IA2019-72 |
| Date of Issue | 2020-02-24 (SITE, IA) |
| Conference Information | |
| Committee | IA / SITE / IPSJ-IOT |
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| Conference Date | 2020/3/2(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagoya University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Internet and Information Ethics Education, etc. |
| Chair | Hiroyuki Osaki(Kwansei Gakuin Univ.) / Tetsuya Morizumi(Kanagawa Univ.) |
| Vice Chair | Rei Atarashi(IIJ) / Toru Kondo(Hiroshima Univ.) / Hiroshi Yamamoto(Ritsumeikan Univ.) / Masaru Ogawa(Kobe Gakuin Univ.) / Takushi Otani(Kibi International Univ.) |
| Secretary | Rei Atarashi(Kwansei Gakuin Univ.) / Toru Kondo(KDDI Research) / Hiroshi Yamamoto(NEC) / Masaru Ogawa(Toyo Eiwa Univ.) / Takushi Otani(KDDI Research) |
| Assistant | Kenji Ohira(Osaka Univ.) / Daiki Nobayashi(Kyushu Inst. of Tech.) / Ryohei Banno(Tokyo Inst. of Tech.) / Nobuyuki Yoshinaga(Yamaguchi Pref Univ.) / Daisuke Suzuki(Hokuriku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Internet Architecture / Technical Committee on Social Implications of Technology and Information Ethics / Special Interest Group on Internet and Operation Technology |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A design and implementation of an HBM-based packet scheduler |
| Sub Title (in English) | |
| Keyword(1) | Internet |
| Keyword(2) | Packet Scheduler |
| Keyword(3) | Memory Technology |
| 1st Author's Name | Katsushi Kobayashi |
| 1st Author's Affiliation | The University of Tokyo(U. Tokyo) |
| Date | 2020-03-03 |
| Paper # | SITE2019-94,IA2019-72 |
| Volume (vol) | vol.119 |
| Number (no) | SITE-434,IA-435 |
| Page | pp.pp.87-92(SITE), pp.87-92(IA), |
| #Pages | 6 |
| Date of Issue | 2020-02-24 (SITE, IA) |