Presentation	2020-03-06 A Study of FPGA Architectures for Deep Neural Network in Control devices Ryo Yamamoto, Hidetomo Iwagawa, Yoshihiro Ogawa,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)
Paper #	VLD2019-135,HWS2019-108
Date of Issue	2020-02-26 (VLD, HWS)

Conference Information
Committee	HWS / VLD
Conference Date	2020/3/4(4days)
Place (in Japanese)	(See Japanese page)
Place (in English)	Okinawa Ken Seinen Kaikan
Topics (in Japanese)	(See Japanese page)
Topics (in English)	Design Technology for System-on-Silicon, Hardware Security, etc.
Chair	Shinichi Kawamura(Toshiba) / Nozomu Togawa(Waseda Univ.)
Vice Chair	Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Daisuke Fukuda(Fujitsu Labs.)
Secretary	Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Daisuke Fukuda(Univ. of Aizu)
Assistant	/ Kazuki Ikeda(Hitachi)

Paper Information
Registration To	Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Study of FPGA Architectures for Deep Neural Network in Control devices
Sub Title (in English)
Keyword(1)
1st Author's Name	Ryo Yamamoto
1st Author's Affiliation	Mitsubishi Electric(Mitsubishi Electric)
2nd Author's Name	Hidetomo Iwagawa
2nd Author's Affiliation	Mitsubishi Electric(Mitsubishi Electric)
3rd Author's Name	Yoshihiro Ogawa
3rd Author's Affiliation	Mitsubishi Electric(Mitsubishi Electric)
Date	2020-03-06
Paper #	VLD2019-135,HWS2019-108
Volume (vol)	vol.119
Number (no)	VLD-443,HWS-444
Page	pp.pp.239-244(VLD), pp.239-244(HWS),
#Pages	6
Date of Issue	2020-02-26 (VLD, HWS)