| Presentation | 2020-02-26 Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing Tomoki Aono, Norihiro Nakaoka, Shyu Saikou, Wang Senling, Higami Yoshinobu, Hiroshi Takahashi, Hiroyuki Iwata, Youichi Maeda, Jun Matsushima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For guaranteeing the functional safety of an in-vehicle system, a power-on self-test (POST) is required to test the devices of system with high fault coverage (e.g.: >90% for stuck-at faults) and within extremely limited test application time TAT (e.g.: <50ms) at the system startup. Multi-cycle test looks promising a way to satisfy these requirements of POST, however, faces a challenge of fault detection degradation (FDD) problem that would obstruct the further test reduction of multi-cycle test. This paper propose a test point insertion approach to address such problem for improving the testability of CUT (circuit under test) in multi-cycle test scheme. In the proposed approach, we also proposed the selection algorithm to determine the most effective location for test point insertion in consideration of the testability of the time-expanded logic circuit under multi-cycle test. We show the effectiveness of the proposed method by an evaluation experiments on benchmark circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | POST / LBIST / Multi-cycle Test / Functional Safety / ISO26262 |
| Paper # | DC2019-89 |
| Date of Issue | 2020-02-19 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2020/2/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Vice Chair | Hiroshi Takahashi(Ehime Univ.) |
| Secretary | Hiroshi Takahashi(Nihon Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing |
| Sub Title (in English) | |
| Keyword(1) | POST |
| Keyword(2) | LBIST |
| Keyword(3) | Multi-cycle Test |
| Keyword(4) | Functional Safety |
| Keyword(5) | ISO26262 |
| 1st Author's Name | Tomoki Aono |
| 1st Author's Affiliation | Ehime Univercity(Ehime Univ.) |
| 2nd Author's Name | Norihiro Nakaoka |
| 2nd Author's Affiliation | Ehime Univercity(Ehime Univ.) |
| 3rd Author's Name | Shyu Saikou |
| 3rd Author's Affiliation | Ehime Univercity(Ehime Univ.) |
| 4th Author's Name | Wang Senling |
| 4th Author's Affiliation | Ehime Univercity(Ehime Univ.) |
| 5th Author's Name | Higami Yoshinobu |
| 5th Author's Affiliation | Ehime Univercity(Ehime Univ.) |
| 6th Author's Name | Hiroshi Takahashi |
| 6th Author's Affiliation | Ehime Univercity(Ehime Univ.) |
| 7th Author's Name | Hiroyuki Iwata |
| 7th Author's Affiliation | Renesas Electronics Corporation(Renesas) |
| 8th Author's Name | Youichi Maeda |
| 8th Author's Affiliation | Renesas Electronics Corporation(Renesas) |
| 9th Author's Name | Jun Matsushima |
| 9th Author's Affiliation | Renesas Electronics Corporation(Renesas) |
| Date | 2020-02-26 |
| Paper # | DC2019-89 |
| Volume (vol) | vol.119 |
| Number (no) | DC-420 |
| Page | pp.pp.19-24(DC), |
| #Pages | 6 |
| Date of Issue | 2020-02-19 (DC) |