| Presentation | 2020-02-26 Soft Error Tolerance of Power-Supply-Noise Hardened Latches Yuya Kinoshita, Yukiya Miura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, with the scaling down and low-power operation of VLSI circuits, reliability degradation due to soft errors has become a problem. Previously, its effect was only problem with space-related equipment such as satellites. However, recently, failures due to soft errors have become obvious problem on the earth, then countermeasures are required. In our previous study, new FF circuits which are countermeasures for power supply noise have been developed. The authors focused on the fact that its latch circuit (Half-Duplex latch) has a partially redundant circuit structure, so we evaluated its soft error tolerance. From results of HSPICE simulation, it is shown that this latch is not only tolerant to power supply noise but also soft error, and the proposed latch shows high-reliability for them. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft Error / Latch / Bit-Flip / Half-Duplex / Clocked Inverter / Transmission Gate |
| Paper # | DC2019-97 |
| Date of Issue | 2020-02-19 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2020/2/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Vice Chair | Hiroshi Takahashi(Ehime Univ.) |
| Secretary | Hiroshi Takahashi(Nihon Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Soft Error Tolerance of Power-Supply-Noise Hardened Latches |
| Sub Title (in English) | |
| Keyword(1) | Soft Error |
| Keyword(2) | Latch |
| Keyword(3) | Bit-Flip |
| Keyword(4) | Half-Duplex |
| Keyword(5) | Clocked Inverter |
| Keyword(6) | Transmission Gate |
| 1st Author's Name | Yuya Kinoshita |
| 1st Author's Affiliation | Tokyo Metropolitan University(Tokyo Metropolitan Univ.) |
| 2nd Author's Name | Yukiya Miura |
| 2nd Author's Affiliation | Tokyo Metropolitan University(Tokyo Metropolitan Univ.) |
| Date | 2020-02-26 |
| Paper # | DC2019-97 |
| Volume (vol) | vol.119 |
| Number (no) | DC-420 |
| Page | pp.pp.67-72(DC), |
| #Pages | 6 |
| Date of Issue | 2020-02-19 (DC) |