Presentation 2020-02-26
A controller augmentation method to reduce the number of untestable faults for multiplexers with n-inputs
Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) With the complexity for VLSIs, transition fault testing is required. However, VLSIs generally have more untestable transition faults than untestable stuck at faults due to the circuit structures. From the view point of structural testing, transition fault coverage might be insufficient and potential timing defects might be escaped. Therefore, design-for-testability to improve transition fault coverage is important. In this paper, we propose LOC test generation models to test control signal lines of multiplexers with n-inputs. The assignments of control signals for the LOC test generation models are realized by controller augmentation. Our experimental results for high-level benchmark circuits show that the proposed method achieved 100% fault coverage for transition faults in the data-paths.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) controller augmentation / test sensitization states / multiplexers / launch on capture
Paper # DC2019-90
Date of Issue 2020-02-19 (DC)

Conference Information
Committee DC
Conference Date 2020/2/26(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
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Topics (in English)
Chair Satoshi Fukumoto(Tokyo Metropolitan Univ.)
Vice Chair Hiroshi Takahashi(Ehime Univ.)
Secretary Hiroshi Takahashi(Nihon Univ.)

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A controller augmentation method to reduce the number of untestable faults for multiplexers with n-inputs
Sub Title (in English)
Keyword(1) controller augmentation
Keyword(2) test sensitization states
Keyword(3) multiplexers
Keyword(4) launch on capture
1st Author's Name Yuki Takeuchi
1st Author's Affiliation Nihon University(Nihon Univ.)
2nd Author's Name Toshinori Hosokawa
2nd Author's Affiliation Nihon University(Nihon Univ.)
3rd Author's Name Hiroshi Yamazaki
3rd Author's Affiliation Nihon University(Nihon Univ.)
4th Author's Name Masayoshi Yoshimura
4th Author's Affiliation Kyoto Sangyo University(Kyoto Sangyo Univ.)
Date 2020-02-26
Paper # DC2019-90
Volume (vol) vol.119
Number (no) DC-420
Page pp.pp.25-30(DC),
#Pages 6
Date of Issue 2020-02-19 (DC)