| Presentation | 2020-01-17 [Poster Presentation] Methodology for Automating Data Feedback Circuit Synthesis for a 4- bit Counter in Adiabatic Quantum-Flux-Parametron Logic Ro Saito, Christopher L. Ayala, Olivia Chen, Tomoyuki Tanaka, Tomohiro Tamura, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Adiabatic quantum-flux-parametron (AQFP) logic is one kind of superconducting logic family spotlighted as a technological foundation for developing extremely low-energy computers. Although AQFP circuits have the advantage of energy consumption, it was not possible to directly apply CMOS EDA tools for generating AQFP circuits due to fundamental circuit structure differences. We have been developing a top-down tool for AQFP circuits to solve this problem. A recent study demonstrated that the developed top-down tool can generate combinational logic circuits automatically. As a next step, we plan to include data feedback loops into the top-down methodology. We show a systematic approach to synchronize the clocks of gates while considering the structural differences of CMOS and AQFP. Each AQFP gate is driven by a quad-phase clock, and signal transmission occurs between gates at every clock phase. The clock phase for each gate is determined by its depth relative to the entire circuit. It is found that the re-timing of a 4-bit counter is possible by finding a maximum delay path and equalizing all paths to the critical delay. A control signal `enable' behaves like the external system clock in CMOS and its activation interval depends on the critical delay. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Logic synthesis / sequential circuit / Topdown / QFPL |
| Paper # | SCE2019-58 |
| Date of Issue | 2020-01-09 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2020/1/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Kohjiro(AIST) |
| Vice Chair | |
| Secretary | (Yokohama National Univ.) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Poster Presentation] Methodology for Automating Data Feedback Circuit Synthesis for a 4- bit Counter in Adiabatic Quantum-Flux-Parametron Logic |
| Sub Title (in English) | |
| Keyword(1) | Logic synthesis |
| Keyword(2) | sequential circuit |
| Keyword(3) | Topdown |
| Keyword(4) | QFPL |
| 1st Author's Name | Ro Saito |
| 1st Author's Affiliation | Electrical and Computer Engineering, Yokohama National University(YNU) |
| 2nd Author's Name | Christopher L. Ayala |
| 2nd Author's Affiliation | Institute of Advanced Sciences, Yokohama National University(YNU IAS) |
| 3rd Author's Name | Olivia Chen |
| 3rd Author's Affiliation | Institute of Advanced Sciences, Yokohama National University(YNU IAS) |
| 4th Author's Name | Tomoyuki Tanaka |
| 4th Author's Affiliation | Electrical and Computer Engineering, Yokohama National University(YNU) |
| 5th Author's Name | Tomohiro Tamura |
| 5th Author's Affiliation | Electrical and Computer Engineering, Yokohama National University(YNU) |
| 6th Author's Name | Nobuyuki Yoshikawa |
| 6th Author's Affiliation | Electrical and Computer Engineering, Yokohama National University(YNU) |
| Date | 2020-01-17 |
| Paper # | SCE2019-58 |
| Volume (vol) | vol.119 |
| Number (no) | SCE-369 |
| Page | pp.pp.117-119(SCE), |
| #Pages | 3 |
| Date of Issue | 2020-01-09 (SCE) |