| Presentation | 2020-01-24 Partial synthesis method based on Column-wise verification for integer multipliers Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Partial logic synthesis is a method that most parts of the target circuits are fixed and the missing portions can be logic synthesized from the large numbers of selections. By modeling the missing portions with Look Up Table (LUT), the synthesis and verification problem can be formulated as Quantified Boolean Formulae (QBF). Partial synthesis works well for non-arithmetic circuits, but for integer multipliers it works only if the target circuit and the specification model to be compared are structurally very close. If the target circuit and the specification model to be compared are not close, such as the cases where implementations are gate level and the specification is just arithmetic multiplication symbol, partial logic synthesis can only work up for 12 bits integer multipliers. The reason is that the method must spend most of the time on the equivalence checking of the two circuits and it is very time consuming if the structures are not similar. Now there are interests in synthesis and verification of large size multipliers such as in cryptography. In this paper, we tried to give an improved and proposed method based on the traditional partial synthesis to speed up the process of large integer multipliers. We applied an approach named Column Wise method to do the last step of equivalence checking. The result showed that we can apply our method to 64 bits integer multipliers within 43 seconds. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Partial synthesisColumn-wiseInteger multipliersGr?bner basis |
| Paper # | VLD2019-89,CPSY2019-87,RECONF2019-79 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD / CPSY / IPSJ-ARC |
|---|---|
| Conference Date | 2020/1/22(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yutaka Tamiya(Fujitsu Lab.) / Yuichiro Shibata(Nagasaki Univ.) / Nozomu Togawa(Waseda Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) |
| Secretary | (Univ. Shiga Prefecture) / Kentaro Sano(NTT) / Yoshiki Yamaguchi(Mitsubishi Electric) / Daisuke Fukuda(Hiroshima City Univ.) / Michihiro Koibuchi(e-trees.Japan) / Kota Nakajima(Univ. of Aizu) / (Hitachi) |
| Assistant | / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Kazuki Ikeda(Hitachi) / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Partial synthesis method based on Column-wise verification for integer multipliers |
| Sub Title (in English) | |
| Keyword(1) | Partial synthesisColumn-wiseInteger multipliersGr?bner basis |
| 1st Author's Name | Jian Gu |
| 1st Author's Affiliation | the University of Tokyo(UTokyo) |
| 2nd Author's Name | Amir Masoud Gharehbaghi |
| 2nd Author's Affiliation | the University of Tokyo(UTokyo) |
| 3rd Author's Name | Masahiro Fujita |
| 3rd Author's Affiliation | the University of Tokyo(UTokyo) |
| Date | 2020-01-24 |
| Paper # | VLD2019-89,CPSY2019-87,RECONF2019-79 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-371,CPSY-372,RECONF-373 |
| Page | pp.pp.211-216(VLD), pp.211-216(CPSY), pp.211-216(RECONF), |
| #Pages | 6 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |