| Presentation | 2020-01-17 [Poster Presentation] Study of low power consumption of adiabatic pass transistor decoder for Josephson-CMOS Hybrid Memories Yu Okamoto, Yuki Hironaka, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, superconducting circuits have attracted attention because of the limitation of CMOS circuit technology. However, it is challenging to construct a large-scale memory by only using the superconducting circuit. To overcome this, a Josephson-CMOS hybrid memory using CMOS memory cells has been proposed [1]. In this study, we reduced the energy consumption of the Josephson-CMOS hybrid memory by using an adiabatic CMOS circuit using transmission gates. The adiabatic CMOS concept is adopted in a decoder design, where its energy consumption occupies about 30% of that of the Josephson-CMOS hybrid memory. We investigated the relationship between a phase number of power supplies and the energy efficiency in 8-bit adiabatic CMOS decoders by circuit simulations. We found that a single-phase power supply method is the most efficient in terms of hardware cost and energy efficiency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Josephson-CMOS hybrid memory / adiabatic CMOS circuit / transmission gates / phase number of power supplies |
| Paper # | SCE2019-49 |
| Date of Issue | 2020-01-09 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2020/1/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Kohjiro(AIST) |
| Vice Chair | |
| Secretary | (Yokohama National Univ.) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Poster Presentation] Study of low power consumption of adiabatic pass transistor decoder for Josephson-CMOS Hybrid Memories |
| Sub Title (in English) | |
| Keyword(1) | Josephson-CMOS hybrid memory |
| Keyword(2) | adiabatic CMOS circuit |
| Keyword(3) | transmission gates |
| Keyword(4) | phase number of power supplies |
| 1st Author's Name | Yu Okamoto |
| 1st Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 2nd Author's Name | Yuki Hironaka |
| 2nd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 3rd Author's Name | Nobuyuki Yoshikawa |
| 3rd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| Date | 2020-01-17 |
| Paper # | SCE2019-49 |
| Volume (vol) | vol.119 |
| Number (no) | SCE-369 |
| Page | pp.pp.79-81(SCE), |
| #Pages | 3 |
| Date of Issue | 2020-01-09 (SCE) |