Presentation 2020-01-17
[Poster Presentation] Design of single flux quantum highly-integrated memory cell and its application to lookup table
Takuya Hosoya, Yuki Yamanashi, Nobuyuki Yoshikawa,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This study focuses on a look-up table (LUT) based on a single flux quantum (SFQ) logic circuit. To realize highly-integrated SFQ LUT, we designed a new memory cell, data input of which is performed by applying dc-currents coupled to the cell. We can write the data to the selected memory cell in the 2-D memory cell array by applying both the x- and y-directional dc-currents. The memory cell is an SFQ non-destructive read-out flip-flop (NDRO) with magnetically-coupled data-input structure. Thought data writing and resetting of the designed memory cell are slow, we can implement the highly-integrated LUT using the memory cell because the wiring for the data-input and data-resetting can be drastically simplified compared to the conventional SFQ LUT that used many passive transmission lines(PTL) for data-input and initializing the data stored in the memory cells. We experimentally confirmed the correct operation of designed memory cell with enough bias margin.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SFQ logic circuit / memory cell / lookup table
Paper # SCE2019-43
Date of Issue 2020-01-09 (SCE)

Conference Information
Committee SCE
Conference Date 2020/1/16(2days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Satoshi Kohjiro(AIST)
Vice Chair
Secretary (Yokohama National Univ.)
Assistant Hiroyuki Akaike(Daido Univ.)

Paper Information
Registration To Technical Committee on Superconductive Electronics
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) [Poster Presentation] Design of single flux quantum highly-integrated memory cell and its application to lookup table
Sub Title (in English)
Keyword(1) SFQ logic circuit
Keyword(2) memory cell
Keyword(3) lookup table
1st Author's Name Takuya Hosoya
1st Author's Affiliation Yokomaha National University(Yokohama Natl. Univ.)
2nd Author's Name Yuki Yamanashi
2nd Author's Affiliation Yokomaha National University(Yokohama Natl. Univ.)
3rd Author's Name Nobuyuki Yoshikawa
3rd Author's Affiliation Yokomaha National University(Yokohama Natl. Univ.)
Date 2020-01-17
Paper # SCE2019-43
Volume (vol) vol.119
Number (no) SCE-369
Page pp.pp.57-60(SCE),
#Pages 4
Date of Issue 2020-01-09 (SCE)