| Presentation | 2020-01-24 26-bit 400-neuron 0.3-ksps FORCE Learning FPGA Core for Reservoir Computing koyo Minamikawa, Shunya Suzuki, Megumi Akai-Kasaya, Tetsuya asai, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Reservoir Computing (RC) is a type of Recurrent Neural Network (RNN) and are used for processing time series. Since the learning part is only the weight of the output layer and the amount of calculation is smaller than that of the RNN, the reservoir computing is expected to learn with low power. Inverse matrix is required to learn in an RC, and numerous resources are required to implement the hardware. However, by using FORCE learning [1], calculations can be performed only with matrix operation without using inverse matrix operation. In this study, we implement a dedicated architecture for learning reservoir computing that drives with low power consumption using FORCE learning with FPGA. We designed the architecture to operate on the cheapest possible FPGA. The board was actually created and evaluated from the viewpoint of accuracy and power consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Neural Network / Reservoir Computing / FPGA / Power saving |
| Paper # | NLP2019-98 |
| Date of Issue | 2020-01-16 (NLP) |
| Conference Information | |
| Committee | NLP / NC |
|---|---|
| Conference Date | 2020/1/23(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Miyakojima Marine Terminal |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroaki Kurokawa(Tokyo Univ. of Tech.) / Hayaru Shouno(UEC) |
| Vice Chair | Kiyohisa Natsume(Kyushu Inst. of Tech.) / Kazuyuki Samejima(Tamagawa Univ) |
| Secretary | Kiyohisa Natsume(Nippon Inst. of Tech.) / Kazuyuki Samejima(Kyushu Inst. of Tech.) |
| Assistant | Yutaka Shimada(Saitama Univ.) / Toshikaza Samura(Yamaguchi Univ.) / Takashi Shinozaki(NICT) / Ken Takiyama(TUAT) |
| Paper Information | |
| Registration To | Technical Committee on Nonlinear Problems / Technical Committee on Neurocomputing |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 26-bit 400-neuron 0.3-ksps FORCE Learning FPGA Core for Reservoir Computing |
| Sub Title (in English) | |
| Keyword(1) | Neural Network |
| Keyword(2) | Reservoir Computing |
| Keyword(3) | FPGA |
| Keyword(4) | Power saving |
| 1st Author's Name | koyo Minamikawa |
| 1st Author's Affiliation | Hokkaido University(Hokkaido Univ.) |
| 2nd Author's Name | Shunya Suzuki |
| 2nd Author's Affiliation | Hokkaido University(Hokkaido Univ.) |
| 3rd Author's Name | Megumi Akai-Kasaya |
| 3rd Author's Affiliation | Hokkaido University(Hokkaido Univ.) |
| 4th Author's Name | Tetsuya asai |
| 4th Author's Affiliation | Hokkaido University(Hokkaido Univ.) |
| Date | 2020-01-24 |
| Paper # | NLP2019-98 |
| Volume (vol) | vol.119 |
| Number (no) | NLP-381 |
| Page | pp.pp.67-72(NLP), |
| #Pages | 6 |
| Date of Issue | 2020-01-16 (NLP) |