| Presentation | 2020-01-17 [Poster Presentation] Design and Evaluation of a 32-word by 8-bit Register File Using Adiabatic Quantum Flux Parametron Logic Tomohiro Tamura, Naoki Takeuchi, Christopher Ayala, Yuki Yamanashi, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Extremely energy-efficient logic devices are required for future energy-efficient highperformance computing systems. Superconducting logic families are attractive because their energy consumption is much lower than that of CMOS circuits. We have been developing adiabatic quantum-fluxparametron (AQFP) logic, which is one of the energy-efficient superconducting logic families, to achieve extremly low-power microprocessors. In a previous study, we designed a 16-word by 4-bit register file, which was the largest register file using AQFP logic. In this study, we have achieved even larger register files, which can be reduced the area of a register file by adopting offset buffers and quantum flux parametron latches (QFPLs). We designed a 32word by 8-bit register file with circuit area and junction count of 9.4 mm by 8.2 mm and 18844, respectively. This reveals that a 32-word by 8-bit register file can be implemented in a 10 mm by 10 mm chip. The 32word by 8-bit register file are fabricated using the AIST 10 kA/cm2 Nb high-speed standard process (HSTP). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Superconducting integrated circuitAdiabatic Quantum Flux ParametronRegister FileMemory |
| Paper # | SCE2019-50 |
| Date of Issue | 2020-01-09 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2020/1/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Kohjiro(AIST) |
| Vice Chair | |
| Secretary | (Yokohama National Univ.) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Poster Presentation] Design and Evaluation of a 32-word by 8-bit Register File Using Adiabatic Quantum Flux Parametron Logic |
| Sub Title (in English) | |
| Keyword(1) | Superconducting integrated circuitAdiabatic Quantum Flux ParametronRegister FileMemory |
| 1st Author's Name | Tomohiro Tamura |
| 1st Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 2nd Author's Name | Naoki Takeuchi |
| 2nd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 3rd Author's Name | Christopher Ayala |
| 3rd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 4th Author's Name | Yuki Yamanashi |
| 4th Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 5th Author's Name | Nobuyuki Yoshikawa |
| 5th Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| Date | 2020-01-17 |
| Paper # | SCE2019-50 |
| Volume (vol) | vol.119 |
| Number (no) | SCE-369 |
| Page | pp.pp.83-86(SCE), |
| #Pages | 4 |
| Date of Issue | 2020-01-09 (SCE) |