| Presentation | 2020-01-17 [Poster Presentation] Optimization of a Josephson latching driver using 10-kA/cm2 Nb process for a Josephson-CMOS hybrid memory Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Josephson digital circuits such as single flux quantum circuits have a great potential for future high-end computing systems in terms of their capability of high-speed operation and low power consumption. One of the most critical challenges that Josephson circuits currently have is a memory; there is no reasonable solution for a large-capacity Josephson memory yet, due to the low integration degree and low driving ability of Josephson devices. A Josephson-CMOS hybrid memory is expected as a good solution for Josephson-compatible large-scale memory systems. A Josephson latching driver, which converts an SFQ pulse input to a voltage level signal, is a key component of the Josephson-CMOS hybrid memory. In this study, we conducted parameter optimization of the Josephson latching driver using the 10-kA/cm2 Nb advanced process in National Institute of Advanced Industrial Science and Technology (AIST). The basic structure is following the circuit that was designed and demonstrated in the 2.5-kA/cm2 Nb standard process, where the circuit is composed of a Suzuki stack with 17/16-Josephson junctions and a 4JL gate as a pre-amplifier. Circuit parameters were modified considering improved junction characteristics in high-Jc processes. In order to compensate the low driving ability of Josephson junctions due to its smaller subgap resistance, we increased the load resistance as well as the critical current of the 4JL gate, so that the bias margins of both Suzuki Stack and 4JL gate were increased. In the experiment, the correct operation of a fabricated circuit was obtained at a target frequency of 2 GHz. The correct operation of the circuit with CMOS circuits was also demonstrated at low frequencies. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Josephson latching driverSuzuki stackvoltage driverJosephson-CMOS hybrid memoryJosephson circuit |
| Paper # | SCE2019-47 |
| Date of Issue | 2020-01-09 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2020/1/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Kohjiro(AIST) |
| Vice Chair | |
| Secretary | (Yokohama National Univ.) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Poster Presentation] Optimization of a Josephson latching driver using 10-kA/cm2 Nb process for a Josephson-CMOS hybrid memory |
| Sub Title (in English) | |
| Keyword(1) | Josephson latching driverSuzuki stackvoltage driverJosephson-CMOS hybrid memoryJosephson circuit |
| 1st Author's Name | Yuki Hironaka |
| 1st Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 2nd Author's Name | Yuki Yamanashi |
| 2nd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 3rd Author's Name | Nobuyuki Yoshikawa |
| 3rd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| Date | 2020-01-17 |
| Paper # | SCE2019-47 |
| Volume (vol) | vol.119 |
| Number (no) | SCE-369 |
| Page | pp.pp.73-74(SCE), |
| #Pages | 2 |
| Date of Issue | 2020-01-09 (SCE) |