| Presentation | 2020-01-24 Virtual-Channel Implementation on Communication Circuit of FPGA Cluster by Qsys Interconnect Naohisa Fukase, Akihisa Furuiti, Yasuyuki Miura, Tsukasa-Pierre Nakao, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent days, in order to improve the performance of computer, methods using FPGA have been attracting attention. FPGA clusters, one of the implementation method of FPGAs, are being researched. We are researching the router circuits for FPGA clusters. The router using the Qsys interconnect of Intel FPGA have high flexibility.In this research, we report the implementation method of virtual channel by using Qsys interconnect. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Qsys Interconnect / Avalon-streaming / Interconnection Network |
| Paper # | VLD2019-82,CPSY2019-80,RECONF2019-72 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD / CPSY / IPSJ-ARC |
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| Conference Date | 2020/1/22(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yutaka Tamiya(Fujitsu Lab.) / Yuichiro Shibata(Nagasaki Univ.) / Nozomu Togawa(Waseda Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) |
| Secretary | (Univ. Shiga Prefecture) / Kentaro Sano(NTT) / Yoshiki Yamaguchi(Mitsubishi Electric) / Daisuke Fukuda(Hiroshima City Univ.) / Michihiro Koibuchi(e-trees.Japan) / Kota Nakajima(Univ. of Aizu) / (Hitachi) |
| Assistant | / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Kazuki Ikeda(Hitachi) / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Virtual-Channel Implementation on Communication Circuit of FPGA Cluster by Qsys Interconnect |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Qsys Interconnect |
| Keyword(3) | Avalon-streaming |
| Keyword(4) | Interconnection Network |
| 1st Author's Name | Naohisa Fukase |
| 1st Author's Affiliation | Shonan Institute of Technology(SIT) |
| 2nd Author's Name | Akihisa Furuiti |
| 2nd Author's Affiliation | Shonan Institute of Technology(SIT) |
| 3rd Author's Name | Yasuyuki Miura |
| 3rd Author's Affiliation | Shonan Institute of Technology(SIT) |
| 4th Author's Name | Tsukasa-Pierre Nakao |
| 4th Author's Affiliation | Shonan Institute of Technology(SIT) |
| Date | 2020-01-24 |
| Paper # | VLD2019-82,CPSY2019-80,RECONF2019-72 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-371,CPSY-372,RECONF-373 |
| Page | pp.pp.169-174(VLD), pp.169-174(CPSY), pp.169-174(RECONF), |
| #Pages | 6 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |