| Presentation | 2020-01-23 Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction set architecture, where several CPU designs are provided under BSD licenses. Binary synthesis, a variant of high-level synthesis, can auto-generate hardware from assembly programs or inline assembly codes, and can be used to synthesize interrupt handler written in assebmly language into hardware. This article presents the first binary synthesizer which takes an executable binary codes for RV32IM and synthesizes a hardware module which is functionally equivalent with a CPU that runs the code. A CDFG is generated from a linked executable binary code, from which an RTL description is generated by the conventional high-level synthesis flow. This method can incorporate custum instructions into the synthesis flow, provided they are executed in fixed cycles and the execution units for them are separately designed from the CPU's datapath. From small scale codes consisting of less than 160 instructions, a prototype synthesizer has generated smaller and faster hardware modules than a Rocket Chip. A code containing SIMD add-saturate instruction has been also synthesized to accelerate the resulting hardware. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Binary synthesis / High-level synthesis / RISC-V / Hardware/Software codesign / Embedded systems |
| Paper # | VLD2019-71,CPSY2019-69,RECONF2019-61 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD / CPSY / IPSJ-ARC |
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| Conference Date | 2020/1/22(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yutaka Tamiya(Fujitsu Lab.) / Yuichiro Shibata(Nagasaki Univ.) / Nozomu Togawa(Waseda Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) |
| Secretary | (Univ. Shiga Prefecture) / Kentaro Sano(NTT) / Yoshiki Yamaguchi(Mitsubishi Electric) / Daisuke Fukuda(Hiroshima City Univ.) / Michihiro Koibuchi(e-trees.Japan) / Kota Nakajima(Univ. of Aizu) / (Hitachi) |
| Assistant | / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Kazuki Ikeda(Hitachi) / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Binary Synthesis from RISC-V Executables |
| Sub Title (in English) | |
| Keyword(1) | Binary synthesis |
| Keyword(2) | High-level synthesis |
| Keyword(3) | RISC-V |
| Keyword(4) | Hardware/Software codesign |
| Keyword(5) | Embedded systems |
| 1st Author's Name | Shoki Hamana |
| 1st Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| Date | 2020-01-23 |
| Paper # | VLD2019-71,CPSY2019-69,RECONF2019-61 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-371,CPSY-372,RECONF-373 |
| Page | pp.pp.111-115(VLD), pp.111-115(CPSY), pp.111-115(RECONF), |
| #Pages | 5 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |