| Presentation | 2020-01-23 Design and implementation of a RISC-V soft processor adopting five-stage pipelining Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a RISC-V soft processor adopting five-stage pipelining optimized for FPGAs that support RV32I, the RISC-V basic instruction set. We show critical paths that can cause performance degradation using the configuration of a typical five-stage pipelining processor. In particular, we need to optimize the instruction fetching stage including the branch prediction mechanism. Compared with this configuration of a typical processor, we propose effective optimization methods applied to the proposed processor for improving the operating frequency. We implement this proposed processor in Verilog HDL and evaluate IPC, operating frequency, hardware resource and processor performance. From the evaluation results, the proposed processor achieves an average performance improvement of 27.4% compared with the related research. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft processor / RISC-V / FPGA / RV32I / Five-stage pipelining / Verilog HDL |
| Paper # | VLD2019-73,CPSY2019-71,RECONF2019-63 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD / CPSY / IPSJ-ARC |
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| Conference Date | 2020/1/22(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yutaka Tamiya(Fujitsu Lab.) / Yuichiro Shibata(Nagasaki Univ.) / Nozomu Togawa(Waseda Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) |
| Secretary | (Univ. Shiga Prefecture) / Kentaro Sano(NTT) / Yoshiki Yamaguchi(Mitsubishi Electric) / Daisuke Fukuda(Hiroshima City Univ.) / Michihiro Koibuchi(e-trees.Japan) / Kota Nakajima(Univ. of Aizu) / (Hitachi) |
| Assistant | / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Kazuki Ikeda(Hitachi) / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and implementation of a RISC-V soft processor adopting five-stage pipelining |
| Sub Title (in English) | |
| Keyword(1) | Soft processor |
| Keyword(2) | RISC-V |
| Keyword(3) | FPGA |
| Keyword(4) | RV32I |
| Keyword(5) | Five-stage pipelining |
| Keyword(6) | Verilog HDL |
| 1st Author's Name | Hiromu Miyazaki |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Takuto Kanamori |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Md Ashraful Islam |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 4th Author's Name | Kenji Kise |
| 4th Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2020-01-23 |
| Paper # | VLD2019-73,CPSY2019-71,RECONF2019-63 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-371,CPSY-372,RECONF-373 |
| Page | pp.pp.123-128(VLD), pp.123-128(CPSY), pp.123-128(RECONF), |
| #Pages | 6 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |