| Presentation | 2020-01-23 Design and implementation of a RISC-V computer system running Linux in Verilog HDL Junya Miura, Hiromu Miyazaki, Kenji Kise, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | RISC-V is an instruction set architecture developed at the University of California, Berkeley. Processors using RISC-V can be created and released freely. Because of this, various processor cores and System on Chip have been released so far. However, there are few public RISC-V computer systems that can boot OS and be try easily. Therefore, we implemented a new RISC-V computer system targeting FPGAs in Verilog HDL. This system can be implemented on an FPGA with few hardware resources, and can be used on low cost FPGAs or customized by introducing an accelerator. This paper describes the knowledge gained from the development of this RISC-V computer system and how to use it. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RISC-V / FPGA / Computer System / Linux / Processor / Verilog HDL |
| Paper # | VLD2019-72,CPSY2019-70,RECONF2019-62 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD / CPSY / IPSJ-ARC |
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| Conference Date | 2020/1/22(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yutaka Tamiya(Fujitsu Lab.) / Yuichiro Shibata(Nagasaki Univ.) / Nozomu Togawa(Waseda Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) |
| Secretary | (Univ. Shiga Prefecture) / Kentaro Sano(NTT) / Yoshiki Yamaguchi(Mitsubishi Electric) / Daisuke Fukuda(Hiroshima City Univ.) / Michihiro Koibuchi(e-trees.Japan) / Kota Nakajima(Univ. of Aizu) / (Hitachi) |
| Assistant | / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Kazuki Ikeda(Hitachi) / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and implementation of a RISC-V computer system running Linux in Verilog HDL |
| Sub Title (in English) | |
| Keyword(1) | RISC-V |
| Keyword(2) | FPGA |
| Keyword(3) | Computer System |
| Keyword(4) | Linux |
| Keyword(5) | Processor |
| Keyword(6) | Verilog HDL |
| 1st Author's Name | Junya Miura |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Hiromu Miyazaki |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Kenji Kise |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2020-01-23 |
| Paper # | VLD2019-72,CPSY2019-70,RECONF2019-62 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-371,CPSY-372,RECONF-373 |
| Page | pp.pp.117-122(VLD), pp.117-122(CPSY), pp.117-122(RECONF), |
| #Pages | 6 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |