| Presentation | 2019-12-23 InP Wafer-level Backside Process for Future Tera-hertz Operation Takuya Tsutsumi, Hiroshi Hamada, Hiroki Sugiyama, Hideyuki Nosaka, Hideaki Matsuzaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The sub-millimeter-wave band would be utilized in future mobile networks to cope with increasing data rates. InP-based SMMIC (Submillimeter-wave monolithic ICs) have attracted much attention because InP-based transistors feature superior RF characteristics. This paper reports wafer-level backside process technology consists of thinning a 3-inch InP wafer, forming dense vias, backside metalization with single-level wiring. We also applied the developed backside bias-lines to an actual SMMIC in order to enhance IC layout effectiveness and reduce electric loss of the RF signals. Finally, we successfully demonstrate a power amplifier with the world’s highest level output power of +9.5 dBm up to the 300-GHz range without any degradation of transistor characteristics. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SubmiIIimeter-wave monolithic ICs (SMMICs) / Indium phosphide (InP) / (InP),Wafer-level backside process / backside lines / High electron mobility transistors (HEMTs) / Heterojunction bipolar transistors (HBTs) |
| Paper # | ED2019-82 |
| Date of Issue | 2019-12-16 (ED) |
| Conference Information | |
| Committee | ED |
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| Conference Date | 2019/12/23(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Michihiko Suhara(TMU) |
| Vice Chair | Hiroki Fujishiro(Tokyo Univ. of Science) |
| Secretary | Hiroki Fujishiro(Saga Univ.) |
| Assistant | Junji Kotani(Fjitsu Lab.) / Takuya Tsutsumi(NTT) |
| Paper Information | |
| Registration To | Technical Committee on Electron Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | InP Wafer-level Backside Process for Future Tera-hertz Operation |
| Sub Title (in English) | |
| Keyword(1) | SubmiIIimeter-wave monolithic ICs (SMMICs) |
| Keyword(2) | Indium phosphide (InP) |
| Keyword(3) | (InP),Wafer-level backside process |
| Keyword(4) | backside lines |
| Keyword(5) | High electron mobility transistors (HEMTs) |
| Keyword(6) | Heterojunction bipolar transistors (HBTs) |
| 1st Author's Name | Takuya Tsutsumi |
| 1st Author's Affiliation | Nippon Telegraph and Telephone Corp.(NTT) |
| 2nd Author's Name | Hiroshi Hamada |
| 2nd Author's Affiliation | Nippon Telegraph and Telephone Corp.(NTT) |
| 3rd Author's Name | Hiroki Sugiyama |
| 3rd Author's Affiliation | Nippon Telegraph and Telephone Corp.(NTT) |
| 4th Author's Name | Hideyuki Nosaka |
| 4th Author's Affiliation | Nippon Telegraph and Telephone Corp.(NTT) |
| 5th Author's Name | Hideaki Matsuzaki |
| 5th Author's Affiliation | Nippon Telegraph and Telephone Corp.(NTT) |
| Date | 2019-12-23 |
| Paper # | ED2019-82 |
| Volume (vol) | vol.119 |
| Number (no) | ED-353 |
| Page | pp.pp.23-28(ED), |
| #Pages | 6 |
| Date of Issue | 2019-12-16 (ED) |