Presentation 2019-11-14
Design of an MTJ-Based Multiply-Accumulate Operation Circuit for an Energy-Efficient Binarized Neural Networks
Tomoki Chiba, Masanori Natsui, Takahiro Hanyu,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this paper, we propose a design of a computational unit for multiply-accumulate (MAC) operations and activation functions utilizing a next-generation nonvolatile memory device for binarized neural network hardware. The proposed circuit reduces the memory access cost by embedding nonvolatile memory devices into logic cells. In addition, the proposed circuit performs the accumulation and activation functions at once by a new circuit configuration based on current-mode linear summation. Through an experimental evaluation of the proposed circuit, we show the impact of the proposed design scheme on compact and energy-efficient neural network hardware.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) binarized neural networks / nonvolatile memory / XNOR / bitcounting / variation compensation
Paper # ICD2019-32,IE2019-38
Date of Issue 2019-11-07 (ICD, IE)

Conference Information
Committee VLD / DC / CPSY / RECONF / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2019/11/13(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Ehime Prefecture Gender Equality Center
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2019 -New Field of VLSI Design-
Chair Nozomu Togawa(Waseda Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Yutaka Tamiya(Fujitsu Lab.) / / Hiroshi Inoue(Kyushu Univ.)
Vice Chair Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(Toshiba-memory) / Kazuya Kodama(NII) / Keita Takahashi(Nagoya Univ.)
Secretary Daisuke Fukuda(Univ. of Aizu) / Hiroshi Takahashi(Hitachi) / Michihiro Koibuchi(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Kentaro Sano(Nagoya Inst. of Tech.) / Yoshiki Yamaguchi(Hokkaido Univ.) / Masafumi Takahashi(Hiroshima City Univ.) / Kazuya Kodama(e-trees.Japan) / Keita Takahashi(Tohoku Univ.) / (Socionext) / (NTT) / (NHK)
Assistant Kazuki Ikeda(Hitachi) / / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) / Kyohei Unno(KDDI Research) / Norishige Fukushima(Nagoya Inst. of Tech.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of an MTJ-Based Multiply-Accumulate Operation Circuit for an Energy-Efficient Binarized Neural Networks
Sub Title (in English)
Keyword(1) binarized neural networks
Keyword(2) nonvolatile memory
Keyword(3) XNOR
Keyword(4) bitcounting
Keyword(5) variation compensation
1st Author's Name Tomoki Chiba
1st Author's Affiliation Tohoku University(Tohoku Univ.)
2nd Author's Name Masanori Natsui
2nd Author's Affiliation Tohoku University(Tohoku Univ.)
3rd Author's Name Takahiro Hanyu
3rd Author's Affiliation Tohoku University(Tohoku Univ.)
Date 2019-11-14
Paper # ICD2019-32,IE2019-38
Volume (vol) vol.119
Number (no) ICD-284,IE-285
Page pp.pp.19-24(ICD), pp.19-24(IE),
#Pages 6
Date of Issue 2019-11-07 (ICD, IE)