| Presentation | 2019-11-01 A Study of Hardware Trojan Detection Method using Deep Learning in Asynchronous Circuits Hikaru Inafune, Masashi Imai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There are typically two timing methods in VLSI designs known assynchronous circuits which use a global clock and asynchronous circuits which are based on the request-and-acknowledge handshaking protocols. In this paper, we show the effectiveness of using the appropriate feature values for asynchronous circuits in order to detect asynchronous hardware Trojans based on the deep learning methods at the netlist design phase. We show that the deep learning method to detect synchronous hardware Trojan nets is also effective to detect asynchronous hardware Trojan nets by using asynchronous hardware Trojan circuits at the training phase. We also show that the appropriate feature values to detect asynchronous hardware Trojans have a great potential to increase the performance of the classifiers. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous Circuits / Hardware Trojan / Deep Learning / Hardware Trojan Detection Method |
| Paper # | HWS2019-63,ICD2019-24 |
| Date of Issue | 2019-10-25 (HWS, ICD) |
| Conference Information | |
| Committee | HWS / ICD |
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| Conference Date | 2019/11/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | DNP Namba SS Bld. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Makoto Nagata(Kobe Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Masafumi Takahashi(Toshiba-memory) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Masafumi Takahashi(Tohoku Univ.) |
| Assistant | / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of Hardware Trojan Detection Method using Deep Learning in Asynchronous Circuits |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous Circuits |
| Keyword(2) | Hardware Trojan |
| Keyword(3) | Deep Learning |
| Keyword(4) | Hardware Trojan Detection Method |
| 1st Author's Name | Hikaru Inafune |
| 1st Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 2nd Author's Name | Masashi Imai |
| 2nd Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| Date | 2019-11-01 |
| Paper # | HWS2019-63,ICD2019-24 |
| Volume (vol) | vol.119 |
| Number (no) | HWS-260,ICD-261 |
| Page | pp.pp.35-40(HWS), pp.35-40(ICD), |
| #Pages | 6 |
| Date of Issue | 2019-10-25 (HWS, ICD) |