Presentation 2019-11-01
Physical-level detection approach against hardware Trojans inside semiconductor chips (I)
Shinichi Kawamura, Kentaro Imafuku, Hirofumi Sakane, Yohei Hori, Makoto Nagata, Yuichi Hayashi, Tsutomu Matsumoto,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) It is of great concern that malicious hardware should be inserted inside semiconductor chips and on printed circuit boards. We call such malicious hardware as a hardware Trojan. Since a hardware Trojan has great impact on our society, we have pressing needs for the development of countermeasure against a hardware Trojan. In this paper, we address that it is important to develop a method to efficiently detect a hardware Trojan from a physical IC chip. In addition, we summarize problems we face when we start to analyze a physical IC chip.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Hardware Trojan / Semiconductor Chip / Physical level / Detection
Paper # HWS2019-65,ICD2019-26
Date of Issue 2019-10-25 (HWS, ICD)

Conference Information
Committee HWS / ICD
Conference Date 2019/11/1(1days)
Place (in Japanese) (See Japanese page)
Place (in English) DNP Namba SS Bld.
Topics (in Japanese) (See Japanese page)
Topics (in English) Hardware Security, etc.
Chair Shinichi Kawamura(Toshiba) / Makoto Nagata(Kobe Univ.)
Vice Chair Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Masafumi Takahashi(Toshiba-memory)
Secretary Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Masafumi Takahashi(Tohoku Univ.)
Assistant / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.)

Paper Information
Registration To Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Physical-level detection approach against hardware Trojans inside semiconductor chips (I)
Sub Title (in English)
Keyword(1) Hardware Trojan
Keyword(2) Semiconductor Chip
Keyword(3) Physical level
Keyword(4) Detection
1st Author's Name Shinichi Kawamura
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
2nd Author's Name Kentaro Imafuku
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
3rd Author's Name Hirofumi Sakane
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
4th Author's Name Yohei Hori
4th Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
5th Author's Name Makoto Nagata
5th Author's Affiliation Natonal Institute of Advanced Industrial Science and Technology/Kobe University(AIST/Kobe Univ.)
6th Author's Name Yuichi Hayashi
6th Author's Affiliation Natinal Institute of Advanced Industrial Science and Technology/Nara Institute of Science and Technology(AIST/NAIST)
7th Author's Name Tsutomu Matsumoto
7th Author's Affiliation National Institute of Advance Industrial Science and Technology/Yokohama National University(AIST/YNU)
Date 2019-11-01
Paper # HWS2019-65,ICD2019-26
Volume (vol) vol.119
Number (no) HWS-260,ICD-261
Page pp.pp.47-52(HWS), pp.47-52(ICD),
#Pages 6
Date of Issue 2019-10-25 (HWS, ICD)