| Presentation | 2019-11-01 A Design of Isogeny-Based Cryptographic Hardware Architecture Using Residue Number System Shuto Funakoshi, Rei Ueno, Naofumi Homma, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we will propose an efficient hardware architecture of isogeny-based cryptography. The proposed architecture utilizes the newly designed multiplier over an imaginary finite field with a characteristic of a huge prime (i.e., Fp2 ) to efficiently perform the Fp2 multiplication that occupies most major part of the computation of isogeny-based cryptography. The proposed multiplier is based on an optimized residue number system (Q-RNS) and utilizes Karatsuba method to perform Fp2 multiplications in parallel. In this paper, we evaluate the designed datapath on Xilinx Kintex Ultrascale+, and show the estimation of latency when we realize an isogeny-based cryptography using the proposed multiplier. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Isogeny-based cryptogaphy / Montgomery Residue Number System(RNS) multiplication / Hardware implementation / Post-quantum cryptography |
| Paper # | HWS2019-60,ICD2019-21 |
| Date of Issue | 2019-10-25 (HWS, ICD) |
| Conference Information | |
| Committee | HWS / ICD |
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| Conference Date | 2019/11/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | DNP Namba SS Bld. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Chair | Shinichi Kawamura(Toshiba) / Makoto Nagata(Kobe Univ.) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Masafumi Takahashi(Toshiba-memory) |
| Secretary | Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Masafumi Takahashi(Tohoku Univ.) |
| Assistant | / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Design of Isogeny-Based Cryptographic Hardware Architecture Using Residue Number System |
| Sub Title (in English) | |
| Keyword(1) | Isogeny-based cryptogaphy |
| Keyword(2) | Montgomery Residue Number System(RNS) multiplication |
| Keyword(3) | Hardware implementation |
| Keyword(4) | Post-quantum cryptography |
| 1st Author's Name | Shuto Funakoshi |
| 1st Author's Affiliation | Research Institute of Electrical Communication Tohoku University(RIEC Tohoku Univ.) |
| 2nd Author's Name | Rei Ueno |
| 2nd Author's Affiliation | Research Institute of Electrical Communication Tohoku University(RIEC Tohoku Univ.) |
| 3rd Author's Name | Naofumi Homma |
| 3rd Author's Affiliation | Research Institute of Electrical Communication Tohoku University(RIEC Tohoku Univ.) |
| Date | 2019-11-01 |
| Paper # | HWS2019-60,ICD2019-21 |
| Volume (vol) | vol.119 |
| Number (no) | HWS-260,ICD-261 |
| Page | pp.pp.19-24(HWS), pp.19-24(ICD), |
| #Pages | 6 |
| Date of Issue | 2019-10-25 (HWS, ICD) |