| Presentation | 2019-11-15 A Method of Parallel Computing for Detailed Routing on Ample Areas Yuya Shijo, Kunihiro Fujiyoshi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There are studies that apply parallel computing to routing problems in LSI design, in order to speed up the routing design. However, only a few methods for detailed routing have been published. In this paper, we propose a parallel computing method for detailed routing of LSIs on ample routing areas. Experiments show that our method achieved 1.91x, 3.49x and 4.35x faster on average for 2, 4, and 8 threads, respectively, compared to that of sequential routing with single thread. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | routing / detailed routing / physical design / parallel computing |
| Paper # | VLD2019-50,DC2019-74 |
| Date of Issue | 2019-11-06 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2019/11/13(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ehime Prefecture Gender Equality Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2019 -New Field of VLSI Design- |
| Chair | Nozomu Togawa(Waseda Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Yutaka Tamiya(Fujitsu Lab.) / / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(Toshiba-memory) / Kazuya Kodama(NII) / Keita Takahashi(Nagoya Univ.) |
| Secretary | Daisuke Fukuda(Univ. of Aizu) / Hiroshi Takahashi(Hitachi) / Michihiro Koibuchi(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Kentaro Sano(Nagoya Inst. of Tech.) / Yoshiki Yamaguchi(Hokkaido Univ.) / Masafumi Takahashi(Hiroshima City Univ.) / Kazuya Kodama(e-trees.Japan) / Keita Takahashi(Tohoku Univ.) / (Socionext) / (NTT) / (NHK) |
| Assistant | Kazuki Ikeda(Hitachi) / / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) / Kyohei Unno(KDDI Research) / Norishige Fukushima(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method of Parallel Computing for Detailed Routing on Ample Areas |
| Sub Title (in English) | |
| Keyword(1) | routing |
| Keyword(2) | detailed routing |
| Keyword(3) | physical design |
| Keyword(4) | parallel computing |
| 1st Author's Name | Yuya Shijo |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 2nd Author's Name | Kunihiro Fujiyoshi |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| Date | 2019-11-15 |
| Paper # | VLD2019-50,DC2019-74 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-282,DC-283 |
| Page | pp.pp.179-184(VLD), pp.179-184(DC), |
| #Pages | 6 |
| Date of Issue | 2019-11-06 (VLD, DC) |