| Presentation | 2019-11-14 Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Hardware Trojan detection is important to ensure security of LSIs. If a hardware Trojan is inserted in a signal line of an LSI, delay of signal propagation paths passing through the signal line increase. In this paper, by using the delay increase, we propose a hardware Trojan detection test generation method using the delay deference of a pre-selected pair of independent paths. The proposed method first analyzes the delay amount of the activation path for each detectable transition fault for a given design. Next, a transition fault test pattern that activates a fault along with a path is paired with another test pattern that activates a different fault along with another path guaranteed to be independent of the path. The delay difference of the activation paths is saved as the expected delay difference of the pair. The generated test pattern pair is applied to the LSIs, which are targets of hardware Trojan detection, manufactured based on the design, and the delay of each activation path is measured. Hardware Trojans are detected by comparing the actual delay difference with the expected delay difference. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hardware-Trojan / transition faults / test pattern generation |
| Paper # | VLD2019-46,DC2019-70 |
| Date of Issue | 2019-11-06 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2019/11/13(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ehime Prefecture Gender Equality Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2019 -New Field of VLSI Design- |
| Chair | Nozomu Togawa(Waseda Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Yutaka Tamiya(Fujitsu Lab.) / / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(Toshiba-memory) / Kazuya Kodama(NII) / Keita Takahashi(Nagoya Univ.) |
| Secretary | Daisuke Fukuda(Univ. of Aizu) / Hiroshi Takahashi(Hitachi) / Michihiro Koibuchi(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Kentaro Sano(Nagoya Inst. of Tech.) / Yoshiki Yamaguchi(Hokkaido Univ.) / Masafumi Takahashi(Hiroshima City Univ.) / Kazuya Kodama(e-trees.Japan) / Keita Takahashi(Tohoku Univ.) / (Socionext) / (NTT) / (NHK) |
| Assistant | Kazuki Ikeda(Hitachi) / / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) / Kyohei Unno(KDDI Research) / Norishige Fukushima(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths |
| Sub Title (in English) | |
| Keyword(1) | hardware-Trojan |
| Keyword(2) | transition faults |
| Keyword(3) | test pattern generation |
| 1st Author's Name | Suguru Rikino |
| 1st Author's Affiliation | Oita Univercity(Oita Univ.) |
| 2nd Author's Name | Yushiro Hiramoto |
| 2nd Author's Affiliation | Oita Univercity(Oita Univ.) |
| 3rd Author's Name | Satoshi Ohtake |
| 3rd Author's Affiliation | Oita Univercity(Oita Univ.) |
| Date | 2019-11-14 |
| Paper # | VLD2019-46,DC2019-70 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-282,DC-283 |
| Page | pp.pp.151-155(VLD), pp.151-155(DC), |
| #Pages | 5 |
| Date of Issue | 2019-11-06 (VLD, DC) |