| Presentation | 2019-11-13 A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults Peikun Wang, Amir Masaud Gharehbaghi, Masahiro Fujita, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a new ATPG-based logic optimization method by removing the redundant multiple faults. In order to find the redundant multiple faults, the incremental ATPG method is applied to quickly filter out the non-redundant faults. The multiple redundancies are eliminated from higher cardinality to lower cardinality; and hence, more redundancies can be removed. The experimental results up to redundant triple faults indicate that the proposed method can remove more redundancy comparing to the redundancy removal command in the synthesis tool SIS. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | logic optimizationredundant multiple faultsincremental fault selection method |
| Paper # | VLD2019-32,DC2019-56 |
| Date of Issue | 2019-11-06 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2019/11/13(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ehime Prefecture Gender Equality Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2019 -New Field of VLSI Design- |
| Chair | Nozomu Togawa(Waseda Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Yutaka Tamiya(Fujitsu Lab.) / / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(Toshiba-memory) / Kazuya Kodama(NII) / Keita Takahashi(Nagoya Univ.) |
| Secretary | Daisuke Fukuda(Univ. of Aizu) / Hiroshi Takahashi(Hitachi) / Michihiro Koibuchi(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Kentaro Sano(Nagoya Inst. of Tech.) / Yoshiki Yamaguchi(Hokkaido Univ.) / Masafumi Takahashi(Hiroshima City Univ.) / Kazuya Kodama(e-trees.Japan) / Keita Takahashi(Tohoku Univ.) / (Socionext) / (NTT) / (NHK) |
| Assistant | Kazuki Ikeda(Hitachi) / / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) / Kyohei Unno(KDDI Research) / Norishige Fukushima(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults |
| Sub Title (in English) | |
| Keyword(1) | logic optimizationredundant multiple faultsincremental fault selection method |
| 1st Author's Name | Peikun Wang |
| 1st Author's Affiliation | The University of Tokyo(The Univ. of Tokyo) |
| 2nd Author's Name | Amir Masaud Gharehbaghi |
| 2nd Author's Affiliation | The University of Tokyo(The Univ. of Tokyo) |
| 3rd Author's Name | Masahiro Fujita |
| 3rd Author's Affiliation | The University of Tokyo(The Univ. of Tokyo) |
| Date | 2019-11-13 |
| Paper # | VLD2019-32,DC2019-56 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-282,DC-283 |
| Page | pp.pp.19-22(VLD), pp.19-22(DC), |
| #Pages | 4 |
| Date of Issue | 2019-11-06 (VLD, DC) |