Presentation | 2019-11-15 CNNアクセラレータSNACCの実チップ評価 Ryohei Tomura, Takuya Kojima, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | SNACC (Scalable Neuro Accelerator Core with Cubic integration) is an accelerator for deep neural network, which can improve the performance by increasing the number of stacked chips with inductive coupling wireless through chip interface (TCI). The chip implementation and real chip evaluation of SNACC are introduced. It consists of four processing element cores which execute dedicated SIMD instructions, distributed memory modules for storing weight data, and TCI. The real chip evaluation by using Renesas Electronics’ 65nm SOTB (Silicon On Thin Box) CMOS technology appears that a simple CNN LeNet works at 50MHz for all layers with 0.90V supply voltage. The power consumption is less than 10mW. The performance can be enhanced by the forward body biasing about 15% in exchange for about 2mW leakage increasing. Also, SNACC achieved more than 20 times high performance to a MIPS R3000 compatible embedded processor. |
Keyword(in Japanese) | (See Japanese page) |
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Paper # | CPSY2019-49 |
Date of Issue | 2019-11-07 (CPSY) |
Conference Information | |
Committee | VLD / DC / CPSY / RECONF / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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Conference Date | 2019/11/13(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Ehime Prefecture Gender Equality Center |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2019 -New Field of VLSI Design- |
Chair | Nozomu Togawa(Waseda Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Yutaka Tamiya(Fujitsu Lab.) / / Hiroshi Inoue(Kyushu Univ.) |
Vice Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(Toshiba-memory) / Kazuya Kodama(NII) / Keita Takahashi(Nagoya Univ.) |
Secretary | Daisuke Fukuda(Univ. of Aizu) / Hiroshi Takahashi(Hitachi) / Michihiro Koibuchi(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Kentaro Sano(Nagoya Inst. of Tech.) / Yoshiki Yamaguchi(Hokkaido Univ.) / Masafumi Takahashi(Hiroshima City Univ.) / Kazuya Kodama(e-trees.Japan) / Keita Takahashi(Tohoku Univ.) / (Socionext) / (NTT) / (NHK) |
Assistant | Kazuki Ikeda(Hitachi) / / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) / Kyohei Unno(KDDI Research) / Norishige Fukushima(Nagoya Inst. of Tech.) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
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1st Author's Name | Ryohei Tomura |
1st Author's Affiliation | Keio University(Keio Univ.) |
2nd Author's Name | Takuya Kojima |
2nd Author's Affiliation | Keio University(Keio Univ.) |
3rd Author's Name | Hideharu Amano |
3rd Author's Affiliation | Keio University(Keio Univ.) |
4th Author's Name | Ryuichi Sakamoto |
4th Author's Affiliation | The University of Tokyo(UTokyo) |
5th Author's Name | Masaaki Kondo |
5th Author's Affiliation | The University of Tokyo(UTokyo) |
Date | 2019-11-15 |
Paper # | CPSY2019-49 |
Volume (vol) | vol.119 |
Number (no) | CPSY-286 |
Page | pp.pp.65-70(CPSY), |
#Pages | 6 |
Date of Issue | 2019-11-07 (CPSY) |