| Presentation | 2019-11-14 FPGA implementation of ISA-based sparse CNN using Wide-SIMD Akira Jinguji, Shimpei Sato, Hiroki Nakahara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Convolutional Neural Network (CNN) achieves high recognition performance in image recognition, and is expected to be applied in embedded systems such as automobiles and security cameras. Embedded systems are required to be realized with inexpensive devices and to have excellent power performance. In image recognition, CNN achieves a discrimination accuracy much higher than that of existing methods, but the CPU cannot realize real-time processing and the GPU consumes too much power. Computational power is inferior to GPU. There is weight sparseness as a method for speeding up CNN. In weighted sparse CNN, most of the parameters are zero, and the product-sum operation including zero accounts for the majority. In order to calculate the weighted sparse CNN at high speed, it is necessary to skip the multiply-add operation including zero, but to skip zero calculation, random access to the memory is required. Random access is generally slower than sequential access. In particular, because GPUs have slow random access, zero skipping is a bottleneck in CNN calculations. In this paper, we propose an FPGA implementation method of CNN calculation that efficiently performs zero skipping using Wide-SIMD. We think that CNN inference can be performed at high speed by using a SIMD-type arithmetic array and on-chip memory as a wide-band buffer. The circuit was designed using Xilinx Vivado HLS and implemented on Digilent PYNQ-Z1. As a result of the experiment, a speed of 86 image/s was achieved with VGG-based YOLOv2. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CNN / FPGA |
| Paper # | RECONF2019-37 |
| Date of Issue | 2019-11-07 (RECONF) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2019/11/13(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ehime Prefecture Gender Equality Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2019 -New Field of VLSI Design- |
| Chair | Nozomu Togawa(Waseda Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Yutaka Tamiya(Fujitsu Lab.) / / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(Toshiba-memory) / Kazuya Kodama(NII) / Keita Takahashi(Nagoya Univ.) |
| Secretary | Daisuke Fukuda(Univ. of Aizu) / Hiroshi Takahashi(Hitachi) / Michihiro Koibuchi(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Kentaro Sano(Nagoya Inst. of Tech.) / Yoshiki Yamaguchi(Hokkaido Univ.) / Masafumi Takahashi(Hiroshima City Univ.) / Kazuya Kodama(e-trees.Japan) / Keita Takahashi(Tohoku Univ.) / (Socionext) / (NTT) / (NHK) |
| Assistant | Kazuki Ikeda(Hitachi) / / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) / Kyohei Unno(KDDI Research) / Norishige Fukushima(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA implementation of ISA-based sparse CNN using Wide-SIMD |
| Sub Title (in English) | |
| Keyword(1) | CNN |
| Keyword(2) | FPGA |
| 1st Author's Name | Akira Jinguji |
| 1st Author's Affiliation | Tokyo Institute of Technology(Titech) |
| 2nd Author's Name | Shimpei Sato |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Titech) |
| 3rd Author's Name | Hiroki Nakahara |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Titech) |
| Date | 2019-11-14 |
| Paper # | RECONF2019-37 |
| Volume (vol) | vol.119 |
| Number (no) | RECONF-287 |
| Page | pp.pp.9-14(RECONF), |
| #Pages | 6 |
| Date of Issue | 2019-11-07 (RECONF) |